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| this is information on a product in full production. march 2013 8209023 rev 5 1/107 1 vx6953cb 5.1 megapixel edof camera module datasheet - production data features ? extended depth of field (edof) technology ? data formats: raw8, raw10 and 10-8 compressed ? smia profile 2 compliant ? mipi csi-2 (d-phy v1.0 compliant) and smia ccp2 video data interface ? maximum data rate: 640 mbps for ccp2 and 800 mbps for csi-2 ? 100 khz to 400 khz cci command interface ? emc shielding ? ultra low power standby mode, 30 w (typ.) ? binning modes (2 x 2) ? hd video formats (1080p30, 720p30) ? pixel defect correction ? nine terms lens shading corrections, bi-cubic correction data available ? 512-byte nvm memory for calibration description the vx6953cb camera module is designed for use across a range of mobile phone handsets and accessories. it embeds high quality still camera functions and also supports hd video. the vx6953cb produces raw bayer 5 mpixel images at 15 fps in raw10. it supports the cci control as well as ccp 2.0 and csi-2 data interfaces. the module design is optimized for both footprint and height. it provides excellent image quality at focus distances from 15 cm in ?super macro mode? (bar code) and from 40 cm to infinity in ?normal mode?. a separate hardware accelerator device (for example, an stv0987) can be integrated in the phone system to run the associated image processing algorithms in hardware where the baseband cannot support this processing load. the sensor is designed to work with any other host with a mipi or smia interface. www.st.com
contents vx6953cb 2/107 8209023 rev 5 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 vx6953cb use in a system with a hardware coprocessor . . . . . . . . . . . . 12 1.2 vx6953cb use in a system with software image processing . . . . . . . . . 13 1.3 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 analog video block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 digital video block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.1 dark calibration algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 device operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.1 power off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.2 hardware standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.3 software standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.4 streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.1 power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.2 power-down procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4.3 internal power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.4 failsafe signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5 clock and frame rate timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.1 video frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.2 pll and clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.3 clock input type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6 control and video interface formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.1 ccp serial data link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.2 csi-2 serial data link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6.3 cci serial control bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 status registers [0x0000 to 0x000f] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8209023 rev 5 3/107 vx6953cb contents 4.2 frame format description registers [0x0040 to 0x007f] . . . . . . . . . . . . . . 30 4.3 analog gain description registers [0x0080 to 0x0097] . . . . . . . . . . . . . . . 31 4.4 data format description registers [0x00c0 to 0x00ff] . . . . . . . . . . . . . . . 32 4.5 setup registers [0x0100 to 0x01ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.6 integration time and gain registers [0x0200 to 0x02ff] . . . . . . . . . . . . . . 34 4.7 video timing registers [0x0300 to 0x03ff] . . . . . . . . . . . . . . . . . . . . . . . . 35 4.8 image scaling registers [0x0400 to 0x04ff] . . . . . . . . . . . . . . . . . . . . . . 36 4.9 image compression registers [0x0500 to 0x05ff] . . . . . . . . . . . . . . . . . . 37 4.10 test pattern registers [0x0600 to 0x06ff] . . . . . . . . . . . . . . . . . . . . . . . . 37 4.11 fifo water mark [0x0700 to 0x0701] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.12 dphy [0x0810 to 0x0811] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.13 binning [0x0900 to 0x0902] and [0x170c to 0x1719] . . . . . . . . . . . . . . . . 38 4.14 shading correction [0x0b00] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.15 defect correction [0x0b05 to 0x0b09] . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.16 edof [0x0b80 to 0x0b8a] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.17 color feedback registers [0x0b8c to 0x0b95] . . . . . . . . . . . . . . . . . . . . . 40 4.18 integration time and gain parameter limit registers [0x1000 to 0x10ff] . 41 4.19 video timing parameter limit registers [0x1100 to 0x11ff] . . . . . . . . . . . . 42 4.20 image scaling parameter limit registers [0x1200 to 0x120b] . . . . . . . . . . 46 4.21 image compression parameter registers [0x1300 to 0x13ff] . . . . . . . . . 46 4.22 csi lane mode capability [0x1600 to 0x1602] . . . . . . . . . . . . . . . . . . . . . 46 4.23 binning capability [0x1700 to 0x170b] . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.24 manufacturer specific registers - clipper 1 [0x31e8 to 0x31eb] . . . . . . . 47 5 video data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.1 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6 video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1 output size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1.1 programmable addressable region of the pixel array . . . . . . . . . . . . . . 51 6.1.2 programmable width and height for outpu t image data . . . . . . . . . . . . . 52 6.1.3 scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.4 subsampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.5 binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 contents vx6953cb 4/107 8209023 rev 5 6.2 video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.2.1 pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.2.2 spread spectrum clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.2.3 framerate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.2.4 derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3 bayer pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.4 image compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.5 exposure and gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.5.1 analogue gain model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.5.2 digital gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.5.3 integration and gain parameter retiming . . . . . . . . . . . . . . . . . . . . . . . . 66 7 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1 schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.2 personality file and firmware updates . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8 edof control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.1 edof capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8.2 control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.3 edof control registers [0x0b80 to 0x0b8a] . . . . . . . . . . . . . . . . . . . . . . 71 8.3.1 edof_mode (0xb80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.3.2 edof_est_focus_distance (0x0b82) . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.3.3 edof tuning sliders (0xb83 to 0x0b85) . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.3.4 edof focus distance (0x0b88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.3.5 edof estimation control (0x0b8a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.4 supermacro mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.5 video modes and edof . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.6 edof and white balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9 image optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.1 defect categorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.1.1 pixel defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.1.2 sensor array area definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.1.3 pixel fault numbering convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.1.4 single pixel faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.1.5 couplet definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8209023 rev 5 5/107 vx6953cb contents 9.1.6 physical aberrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.2 defect correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.3 mapped couplet correction (bruce) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.4 green imbalance correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.5 lens shading correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 10 nvm contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.1 green imbalance corrector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.2 lens shading gridiron correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.3 sensitivity data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.4 nvm map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11 emc recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.3 power supply - vdig, vana . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.3.1 power supply (peak current) - vdig, vana . . . . . . . . . . . . . . . . . . . . . . 92 12.3.2 power supply ripple requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12.4 system clock - extclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 12.5 power down control - xshutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 12.6 cci interface - sda, scl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 12.6.1 cci interface - dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 12.6.2 cci interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 12.7 ccp interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.7.1 ccp interface - dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.7.2 ccp interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.8 csi-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.8.1 csi-2 interface - dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.8.2 csi-2 interface - ac specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13 optical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.1 lens characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.2 text, 1d and 2d codes reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 contents vx6953cb 6/107 8209023 rev 5 14 mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 14.1 packaging and delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 14.2 inner box labelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 14.3 packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 14.4 module outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 15 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 16 user precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 17 acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8209023 rev 5 7/107 vx6953cb list of tables list of tables table 1. technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2. reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. power management matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. power-up sequence timing constraints for ccp 2/csi2 communications . . . . . . . . . . . . . . 20 table 6. power-down sequence timing constraints for csi2 communications . . . . . . . . . . . . . . . . . 23 table 7. por cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8. system input clock frequency range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 table 9. status registers [0x0000 to 0x000f] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 10. frame format description registers [0x0040 to 0x00 7f] . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 11. analog gain description [0x0080 to 0x0093] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 12. data format description registers [0x00c0 to 0x00ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 13. setup registers [0x0100 to 0x01ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 14. integration time and gain registers [0x0200 to 0x02 ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. video timing registers [0x0300 to 0x03ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 16. image scaling registers [0x0400 to 0x04ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. image compression registers [0x0500 to 0x05ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. test pattern registers [0x0600 to 0x06ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 19. fifo water mark registers [0x0700 to 0x0701]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 20. dphy registers [0x0810 to 0x0811] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 table 21. binning registers [0x0900 to 0x0902] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 22. shading correction registers [0x0b00] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 23. defect correction registers [0x0b05 to 0x0b09] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 24. edof registers [0x0b80 to 0x0b8a] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 25. color feedback registers [0x0b8c to 0x0b95] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 26. integration time and gain parameter limit registers [0x1000 to 0x10ff]. . . . . . . . . . . . . . . 41 table 27. video timing parameter limit registers [0x1100 to 0x11ff]. . . . . . . . . . . . . . . . . . . . . . . . . 42 table 28. image scaling parameter limit registers [0x1200 to 0x120b] . . . . . . . . . . . . . . . . . . . . . . . 46 table 29. image compression parameter limit registers [0x 1300 to 0x13ff] . . . . . . . . . . . . . . . . . . . 46 table 30. csi lane mode capability register s [0x1600 - 0x1602] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 31. binning capability regi sters [0x1700 to 0x170b] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 32. manufacturer specific registers [0x31e8 to 0x31eb] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 33. binning register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 34. external clock frequency examples - 5.0 mpixe l raw10 14.5 fps (csi-2) . . . . . . . . . . . . . 58 table 35. external clock frequency examples - 5.0 mpixe l raw10 15 fps (csi-2) . . . . . . . . . . . . . . 58 table 36. external clock frequency examples - 5.0 mpixe l 10-8 compressed 15 fps . . . . . . . . . . . . . 59 table 37. example - 5.0 mpixel 10-8 compressed 16.65 fps (c si-2) . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 38. external clock frequency examples - 1080x1920 in 10-8 bit @ 30fps (ccp) . . . . . . . . . . . 59 table 39. 720x1280 @ 30 fps in raw10 (csi2/ccp2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 40. analog gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 41. edof registers [0x0b80 to 0x0b8a] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 42. color feedback registers [0x0b8c to 0x0b95] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 43. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 44. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 45. power supplies vdig, vana . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 46. in-rush current vdig, vana for ccp2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 47. in-rush current vdig, vana for csi-2 interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 48. ripple requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 list of tables vx6953cb 8/107 8209023 rev 5 table 49. system clock - extclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 50. power down control - xshutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 51. cci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 52. cci interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 53. ccp interface - dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 54. ccp interface - timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 55. csi-2 interface - high speed mode - dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 56. csi-2 interface - low power mode - dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 57. csi-2 interface - high speed mode - ac specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 58. csi-2 interface - low power mode - ac specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 59. typical lens design characteristics for first sour ce lens supplier . . . . . . . . . . . . . . . . . . . . 99 table 60. qr code (2d)resolution reading capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 61. substrate marking codification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 62. outline drawing informat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 63. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 64. acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 65. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8209023 rev 5 9/107 vx6953cb list of figures list of figures figure 1. vx6953cb in system with processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. vx6953cb in a system with software image processi ng . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. vx6953cb module pinout (viewed from bottom of camera module) . . . . . . . . . . . . . . . . . 15 figure 4. overview of analog video block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. system state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. vx6953cb power-up sequence for ccp2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7. vx6953cb power-up sequence for csi-2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. vx6953cb power-down sequence for csi-2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. por timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. clock input types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11. csi serial data link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 12. vx6953cb ccp frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 13. vx6953cb csi-2 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 14. programmable addressable region of the pixel arra y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 15. output size within a ccp data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 16. scaling modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 17. scaler quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 18. example image full scaled by a downscale factor of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 19. subsample readout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 20. binning repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 21. vx6953cb clock relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 22. timing block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 23. smia output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 24. fifo water mark control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 25. bayer pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 26. analogue gain register format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 27. example of a mobile camera application (ccp2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 28. example of a mobile camera application (csi2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 29. what is sharp? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 30. edof main principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 31. focus strategy weightings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 32. processing pipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 33. vx6953cb pixel defect test area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 34. pixel numbering notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 35. single pixel fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 36. general couplet example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 37. test region definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 38. scan array for blemis h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 39. fail map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 40. contiguous pixel example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 41. image showing defective pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 42. block diagram of dynamic defect correction block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 43. dynamic defect correction outp ut example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 44. corrected bayer patter n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 45. green imbalance correction plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 46. lens shading images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 47. cci ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 48. sublvds ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 list of figures vx6953cb 10/107 8209023 rev 5 figure 49. barcode and qr code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 0 figure 50. marking diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8209023 rev 5 11/107 vx6953cb overview 1 overview the vx6953cb image sensor produces raw 5.0 mpixel digital video data at up to 16.5 frames per second. the vx6953cb has both ccp2.0 and mipi csi-2 vi deo data interfaces selectable over the camera control interface (cci). the vx6 953cb is compliant with the smia 1.0 (a) specification profile 2. the vx6953cb can also be used as a profile 0 or profile 1 device. the sensor supports full horizontal and vertical scaling and output frequency derating as defined in the specification. the vx6953cb supports 2 x 2 binning mode which supports 720p30 video format. the image data is digitized using an internal 10 -bit column adc. the re sulting pixel data is output as 8-bit, 10-bit or 10-8 bit compressed data and includes checksums and embedded codes for synchronization. the interface conforms to both the ccp 2.0 and mipi csi-2 interface standards. the sensor is fully conf igurable through a cci serial interface. the module is available in a smop type pa ckage measuring 6.5 x 6.5 x 4.6 mm. it is designed to be used with a board mounted smia65 socket or flex. a. including up to ecr0002. table 1. technical specification feature detail optical format 1/4" pixel resolution 2608 x 1960 (5.0 megapixel) sensor technology img140 sts 65nm based cmos imaging process pixel size 1.4 m x 1.4 m exposure control + 81 db analogue gain + 24 db (max) digital gain + 3 db (max) dynamic range 63 db signal to noise 36 db (@ 100 lux) supply voltages analog: 2.3v to 2.9v (2.8v nom.) digital: 1.7v to 1.9v (1.8v nom.) power consumption <300 mw package size (l x h x w ) 6.5 x 6.5 x 4.6 mm (without lens cover) lens 58 +/-2 hfov f/2.8 relative illumination 75 % (typ.) system attach smia65 socket or flex temperature range normal operating: -25c to +55c storage: -40c to +85c overview vx6953cb 12/107 8209023 rev 5 1.1 vx6953cb use in a system wi th a hardware coprocessor the vx6953cb is an image sensor and it can be paired with either stv0986 or stv0987 stmicroelectronics companion processor. the coprocessor and the sensor together form a complete imag ing system. figure 1 illustrates a typical system using vx6 953cb, a coprocessor and a secondary camera vw6558 (cif + camera for video conferencing). figure 1. vx6953cb in system with processor vx6953cb vw6558 (vga) ccp 2.0 rx ccp 2.0 rx input data i/f output coder mux bayer reconstruc- tion scaler color engine color engine house cci master cci slave keeper stv0986 mobile baseband extclk xshut down xshut down cci cci xshut down cci ccp ccp ccp2 tx cci pixel array and imaging processes imaging processes cci pixel array and or stv0987 ccp2 tx 8209023 rev 5 13/107 vx6953cb overview the sensor main function is to convert the vi ewed scene into a data stream. the companion processor function is to manage the sensor so that it can produce the best possible pictures and to process the data stream into a form which is easily handled by up-stream mobile baseband or multi-media processor (mmp) chipsets. the sensor supplies high-speed clock signals to the processor and provides the embedded control sequences which allow the coprocessor to synchronize with the frame and line level timings. the processor then performs the color processing on the raw image data from the sensor before supplying the final image data to the host. with the coprocessor system, the clock is s ent by host to both the vx6953cb and the coprocessor. the high-speed clock for the copr ocessor is supplied from the vx6953cb. it is generated using the vx6953cb pll and is prov ided as the continuous data qualification clock. 1.2 vx6953cb use in a system wi th software image processing the vx6953cb image sensor can be directly connected to a baseband or multimedia processor. no dedicated coprocessor is used in this configuration. the image processing is done in software or hardware within the baseband processor. figure 2. vx6953cb in a system with software image processing systems with a ccp 2.0 interface can operate with this device, however they may have a maximum ccp link speed of 650 mbps and theref ore will not be able to achieve 15 fps with this device. systems with csi-2 interface (mipi) can operat e with this sensor. with a 800 mbps csi-2 link speed, they can achieve 15 fps in full size image. mobile baseband processor xshutdown extclk smia cci ccp vx6953cb imaging processes cci ccp2 tx pixel array and overview vx6953cb 14/107 8209023 rev 5 1.3 reference documents table 2. reference documents title date smia 1.0 functional specification 30/06/2004 smia 1.0 characterization specification rev a 10/03/2005 smia 1.0 ccp2 spec ification 30/06/2004 smia 1.0 mechanical sp ecification 30/06/2004 smia 1.0 functional specification ecr0001 ver 1 11/02/2005 smia 1.0 ccp2 specification ec r0002 version 1.0 11/02/2005 mipi alliance standard for camera serial interface 2 (csi-2) v1.0 nov 2005 mipi alliance d-phy specification (v00-90-00) oct 2007 8209023 rev 5 15/107 vx6953cb device pinout 2 device pinout figure 3 provides the pin positions and table 3 provides the signal descriptions. figure 3. vx6953cb module pinout (viewed from bottom of camera module) table 3. pin descriptions pad number pad name i/o type description power supplies 1 vcap pwr no connection required (1) 7 gnd pwr ground (combined) 2 vana pwr analog power supply (typically 2.8v) 10 vdig pwr digital power supply (typically 1.8v) system 3 xshutdown i power down control (2) 4 extclk i system clock in put (6 mhz to 27 mhz) (3) 123456 7 8 9 10 11 12 t1 t2 t3 t4 t5 t6 t7 t8 xshutd datan datap vcap vana extclk scl sda vdig clkp clkn gnd orientation key device pinout vx6953cb 16/107 8209023 rev 5 control 5 scl i serial communication clock 6 sda i/o serial communication data data 8 clk- sublvds output output qualifying clock 9 clk+ sublvds output output qualifying clock 11 data- sublvds output serial output data 12 data+ sublvds output serial output data st test t1 to t8 st test pins do not connect (4) 1. vcap is internal to the module. 2. signal is active low. 3. the extclk pad has a schmitt trigger input. 4. test pins are not floating. table 3. pin descriptions (continued) pad number pad name i/o type description 8209023 rev 5 17/107 vx6953cb functional description 3 functional description this chapter details the main blocks in the device: ? analog video block, see section 3.1 ? digital video block, see section 3.2 ? power management, see section 3.4 on page 19 this chapter also describes: ? the device?s operating modes, section 3.3 on page 18 ? clock and frame rate control, see section 3.5 on page 26 ? control and video interface formats, see section 3.6 on page 27 3.1 analog video block 3.1.1 block diagram the analog video block, shown in figure 4 , consists of a 5.0 mpixel resolution pixel array, power management circuitry. the digital block pr ovides all timing signals to drive the analog block. figure 4. overview of analog video block pixel voltage values are read out and digitized using the address decoders and column adc. 5.0 mpixel pixel array y address digital logic raw sensor data timing signals timing signals power management sram readout x-address column adc functional description vx6953cb 18/107 8209023 rev 5 3.2 digital video block the main features of the digital video block are: ? frame rate: 16.65 frame/s maximum can be reduced down to less than 3 frame/s (5.0 mpixel) using frame extension ? automatic dark calibration to ensure consistent video level over varying scenes ? on-chip power-on-reset cell ? output format: 5.0 mpixel 2608 x 1960 (maximum) 3.2.1 dark calibration algorithm the vx6953cb runs a dark calibration algorithm on the raw image data to control the video offsets caused by dark current. this ensures that a high quality image is output over a range of operating conditions. the first frame dark level is correctly calibrated, for subsequent frames the adjustment of the dark level is damped by a leaky integrator function to avoid possible frame to frame flicker. 3.3 device operating modes figure 5. system state diagram power-off csi-2 hw-standby csi-2 sw_standby csi-2 csi-2 streaming sw_standby ccp2 ccp2 streaming power supplies off power supplies off power supplies off power supplies on cci cci cci cci xshutdown xshutdown power supplies off xshutdown is high cci is low xshutdown is low is low power supplies off 8209023 rev 5 19/107 vx6953cb functional description 3.3.1 power off power supplies are off. 3.3.2 hardware standby this is the lowest power consumption mode. cci communications are not supported in this mode. the clock input pad, pll and the vid eo blocks are powered down. this state is entered by pulling the control pin xshutdown down. all registers are returned to their default values. 3.3.3 software standby software standby mode preserves the contents of the cci register map. cci communications are supported in this mode. the software standby mode is selected using a serial interface command. if this state is entered from hardware standby, the data pads remain high impedance. if this state is entered from streaming, then the data pads go high impedance at the end of the current frame. at this point, the video block and pll power down. the internal video timing is reset to the start of a video frame in preparation for the enabling of active video. the values of the se rial interface registers like exposure and gain are preserved. the system clock must remain active when communicating with the sensor. this state is entered by releasing the device from hard reset by: setting xshutdown high, writing 0x00 to the mode control register (0x0100) or commanding a soft reset by writing 0x01 to the software reset register (0x0103). after a soft reset or the transition of xshutdown to high, all registers are returned to their default values. 3.3.4 streaming the vx6953cb streams live video. this mode is entered by writing 0x01 to the mode control register (0x0100). 3.4 power management vx6953cb requires a dual power supply. the analog circuits are powered by a nominal 2.8v supply while the digital logic and digital i/o are powered by a 1.8v supply. different sections of the sensor are powered depending on the system state. see table 4 for details. table 4. power management matrix mode functional block powered down video data inhibit cci digital internal and output clocks (1) 1. pll block and data clk+ and clk- pins output pins analog hardware standby yes yes yes yes yes yes software standby no yes yes yes yes yes streaming no no no no no no functional description vx6953cb 20/107 8209023 rev 5 3.4.1 power-up procedure the digital and analog supply voltages can be powered up in any order for example, vdig then vana or vana then vdig. see table 5 for timing constraints. on power-up the on-chip power-on reset cell ensures that the cci register values are initialized correctly to their default values. the extclk clock can either be initially low and then enabled during software standby mode or extclk can be a free running clock. table 5. power-up sequence timing cons traints for ccp2/csi2 communications symbol parameter min. max. units t0 vana rising ? vdig rising vana and vdig may rise in any order the rising separation can vary from 0 ns to indefinite ns t1 vdig rising ? vana rising ms t2 vana/vdig ? xshutdown rising xshutdown must rise coincident with, or later than, both power supplies (vdig and vana) us t3 xshutdown ? first i 2 c transaction with free running clock 5 (1) 1. 5 ms is necessary to upload the nvm data into firmware registers and get the fw ready for sensor initialization through i 2 c writes. -ms t4 minimum period with extclk present prior to the first i 2 c transaction. gated clock. 5 (2) 2. for gated clock. -ms t5 pll start up/lock time - 1 ms t6 entering streaming mode ? first frame start sequence (fixed part) -10ms t7 entering streaming mode ? first frame start sequence (variable part) = integration time fine_integration_ time_min -ms 8209023 rev 5 21/107 vx6953cb functional description figure 6. vx6953cb power-up sequence for ccp2 mode t0 t1 t3 t4 t5 t6 vdig vana xshutdown extclk (gated) sda scl clkp/- datap/- frame count register extclk may be free running or gated read device id configure device enter streaming high z (tri-state) 0xff 0x00 high z (tri-state) t2 t7 power-off hw- sw-standby streaming this is an example of vana rising after vdig standby extclk (free running) functional description vx6953cb 22/107 8209023 rev 5 figure 7. vx6953cb power-up sequence for csi-2 mode t5 t6 extclk (free running) sda scl clkp/- datap/- frame count register extclk may be free running or gated read device id configure device enter streaming 0xff 0x00 t7 streaming low power low power high-speed tx t0 t1 t3 vdig or vana vana or vdig xshutdown t2 power-off hw- sw-standby standby this is an example of vana rising after vdig t4 extclk (gated) 8209023 rev 5 23/107 vx6953cb functional description 3.4.2 power-down procedure table 6. power-down sequence timing constraints for csi2 communications symbol parameter min. max. units t8 last i 2 c transaction to mipi frame end (1) 1. the whole power down sequence is triggered by the cci power down request, however the power down sequence will only start after the end of the frame when all active data are consumed on csi-2 dn/dp pins. when this is done, the csi-2 dn/dp signals enter lp11. the csi-2 clock will enter lp11 with a delay of 5us (corresponding to tclk_post + tclk_trail) compared to dn/dp pins. the device is then sw_standby and will enter lp00 and stay in ultra low power mode. - 1 frame t9 minimum extclk cycles required after last i 2 c transaction or mipi frame end (2) 2. after the last frame completion, the gated clock needs to be kept for 512 cycles at least so the system can enter ultra low power state. after t he system enters ulps mode, you can keep or stop the extclk. 512 - clock cycles t10 last i 2 c transaction or mipi frame end to xshutdown failling (3) 3. note: xshutdown can be asserted at any time. this immediately removes the core-supply, causing the por to trigger and reset all the digi tal logic and macros - it does not depend on the presence of the clock. when xshutdown is asserted, the clock can be running or not - it does not matter. t8+t9 - t11 xshutdown to vana/vdig falling xshutdown must fall at the same time as, or earlier than, both power supplies (vdig and vana) t12 vana to vdig or vdig to vana falling vana and vdig may fall in any order, the rising separation can vary from 0 ns to indefinite functional description vx6953cb 24/107 8209023 rev 5 figure 8. vx6953cb power-down sequence for csi-2 mode extclk (free running) extclk (gated) sda scl clkp/- datap/- extclk may be free running or gated configure device t8 streaming lp11 high-speed tx t12 t11 vdig xshutdown power-off hw- standby high-speed tx stop streaming t9 vana sw_standby this is an example of vana falling after vdig lp11 t10 ulps ulps ulps ulps undefined (power is off) undefined (power is off) lp00 lp00 8209023 rev 5 25/107 vx6953cb functional description 3.4.3 internal power-on reset (por) the vx6953cb internally performs a power-on reset (por) when the 1v2 vcore digital supply rises through the trigger level, vtrig_rising. similarly, if the 1v2 vcore digital power supply falls through the trigger level, vtrig_falling, then the power-on reset will also trigger. definitions rise threshold voltage (vtrigr) is the supply voltage level th at is recognised by the por as voltage ?high?. only after the supply reaches this level does the output of por change to high level if it is off, af ter a specified amount of delay. fall threshold voltage (vtrigf) is the supply voltage level that is recognised by the por as voltage ?low?. only after the supply reac hes this level does the output of por change to low (ground) level if it is on. burst width (pw) . burst is the negative pulse riding t he supply signal. the burst width is measured as the amount of duration for wh ich the supply signal dropped beyond the threshold levels. delay duration (tpor) is defined as the time duration for which por stays off before repowering. each reset of por will impart a specified delay duration before por repowers. figure 9. por timing table 7. por cell characteristics symbol constraint min typ. max units vtrigr por rise voltage detection - - 0.95 v vtrigf por fall voltage detection 0.4 - - v tburst (pw) burst filter - 2 8 s tpor delay duration - 20 45 s functional description vx6953cb 26/107 8209023 rev 5 3.4.4 failsafe signals all signals going into the vx6953cb must be at either a low state or a high impedance when power is removed from the device. the exceptions to this rule are the extclk, xshutdown and the cci signals. these pads have been designed to be high impedance when the vx6953cb is powered-down. this means that the input signal on the specified pads can either be high or low with no leakage problems. 3.5 clock and frame rate timing 3.5.1 video frame rate control the output frame rate of vx6953cb can be reduced by extending either the line length or the frame length. the extension is achieved by adding extra blanking bytes at the end of a line or ?blank? video lines to act as timing padding. the frame rate can be reduced from the default 15 frame/s at 5.0 mpixel resolution to less than 3 frame/s at 5.0 mpixel resolution. the advantage of the frame extension approach is that it does not reduce the pixel readout rate or the active frame time and therefore do es not introduce unwanted motion distortion effects to the image. 3.5.2 pll and clock input the vx6953cb has an embedded pll block. this block generates all necessary internal clocks from an input range defined in table 8 . the input clock pad accepts up to 27 mhz signals. the input clock can be a sine wave or square wave. table 8. system input clock frequency range min. (mhz) max. (mhz) 6 27 8209023 rev 5 27/107 vx6953cb functional description 3.5.3 clock input type as required by the smia specification the vx6953cb can receive the clock types shown in figure 10 . the clock is fail-safe/high impedance when in either ac or dc coupled and in any mode including the power off state. the pad has a schmitt trigger input. figure 10. clock input types 3.6 control and video interface formats image data is transferred from the vx6953cb using a high speed sublvds serial link.the serial control data is transferred to and from the vx6953cb on a cci bus. ? video maximum link speeed: 640 mbps for ccp2 and 800 mbps for csi-2. ? cci command speed: from 100 khz to 400 khz. 3.6.1 ccp seri al data link data signals (data+ and data-) and clock signals (clk+ and clk-) are transferred from vx6953cb on two pairs of balanced 100 impedance transmission lines. the transmission line pairs and custom transmitters/receivers realize a very low voltage differential (sublvds) signalling scheme that can transfer inform ation in a potentially noisy environment. as implemented in vx6953cb, the ccp link suppor ts the transmission of raw bayer data at 5.0 mpixel resolution up to 11.5 frame/s at 10-bit resolution (with de-rating). pad pad extclk extclk camera module host processor pad pad extclk extclk camera module host processor pad pad extclk extclk camera module host processor pad pad extclk extclk camera module host processor 1st option 2nd option pwrdn pwrdn pwrdn pwrdn pwrdn pwrdn pwrdn pwrdn dc-coupled ac-coupled 3rd option dc-coupled and filtered 4th option ac-coupled and filtered functional description vx6953cb 28/107 8209023 rev 5 3.6.2 csi-2 serial data link data signals (data+ and data-) and clock signals (clk+ and clk-) are transferred from vx6953cb on two pairs of balanced 100 impedance transmission lines. the physical layer of the interface is th e mipi alliance standard d-phy. the transmission line pairs and custom transmitters/receivers realize a very low voltage differential (sublvds) signalling scheme that can transfer inform ation in a potentially noisy environment. as implemented in vx6953cb, the csi-2 link supports the transmission of raw bayer data at 5.0 mpixel resolution up to 15 frame/s at 10-bit resolution and up to 16.65 fps. in 10-8 bit compressed data format. it is to be noted that image quality between raw10 and 10-8 bits format is very similar. figure 11. csi serial data link 3.6.3 cci serial control bus the internal registers in vx6953cb can be configured by a master device using a cci bus (sda, scl). vx6953cb sends and receives commands over this bus at up to 400 kb/s. the cci bus uses a device address of 0x20 for writes and 0x21 for reads. mscl data+ data- clock- clock+ data+ data- clock- clock+ csi rx host csi tx camera transmitter sscl msda ssda cci master cci slave 8209023 rev 5 29/107 vx6953cb register map 4 register map in this chapter the following abbreviations are used in the data type and type columns: 4.1 status registers [0x0000 to 0x000f] ui universal integer sr signed real 32ui 32-bit floating si signed integer ro read only rw read and write ur unsigned real bbit sf signed float table 9. status registers [0x0000 to 0x000f] index byte register name data type default type comment 0x0000 hi model_id 16ui 03.b9 ro camera model identification 0x03b9 = 953 10 0x0001 lo 0x0002 revision_number_major 8ui 00 ro revision identifier of the camera for dcc change 0x0003 manufacturer_id 8ui 01 ro module manufacturer id: st 0x0004 smia_version 8ui 0a ro 0x0a: smia 1.0 0x0005 frame_count 8ui ff ro frame count increments by 1 on each frame. rolls over at 255 to 0. when moving from video to sleep the frame count is reset to 255. the frame count is also reset to 255 after a soft reset (register 0x0103). 0x0006 pixel_order 8ui 00 ro color pixel readout order. defines the order of the color pixel readout. changes with mirror and flip (register 0x0101). 0x00 - gr/bg - normal 0x01 - rg/gb - horizontal mirror 0x02 - bg/gr - vertical flip 0x03 - gb/rg - vertical flip and horizontal mirror 0x0008 hi data_pedestal 16ui 00.40 ro the video data is offset by 64. 0x0009 lo register map vx6953cb 30/107 8209023 rev 5 4.2 frame format description registers [0x0 040 to 0x007f] for a full description of the frame format description, refer to chapter 5: video data interface on page 48 . 0x000c pixel_depth 8ui 0a ro pixel data resolution. 0x0010 revision_number_minor 8ui 00 ro module revision identifier of the camera for minor changes. 0x0016 hi sensor_model_id 16ui 03 ro silicon identification number. this may not be the same as the module identification number, for example, in the case where the same silicon is used in two different modules. 0x0017 lo b9 ro 0x0018 3:0 sensor_revision_number 8ui 00 ro 7:4 02 ro silicon mask revision code. 02 = cut3.0 table 9. status registers [0x0000 to 0x000f] (continued) index byte register name data type default type comment table 10. frame format description registers [0x0040 to 0x007f] index byte register name data type default type comment 0x0040 frame_format_model_type 8ui 01 ro generic frame format. 0x01: 2-byte data format. (1) 0x0041 frame_format_model_subtype 8ui 12 ro contains the number of 2-byte data format descriptors used. upper nibble defines the number of column descriptors that is, 1. the lower nibble defines the number of row descriptors that is, 2. 0x0042 hi frame_format_descriptor_0 16ui 5a.30 ro pixel data code: 5 (visible columns) number of pixels : readout dependent (maximum of 2608) 0x0043 lo 0x0044 hi frame_format_descriptor_1 16ui 10.02 ro pixel data code: 1 (embedded data lines) number of lines: 2 0x0045 lo 0x0046 hi frame_format_descriptor_2 16ui 57.a8 ro pixel data code: 5 (visible lines) number of lines: readout dependent (maximum of 1960) 0x0047 lo 1. see section 4.5 of smia 1.0 functional specification. 8209023 rev 5 31/107 vx6953cb register map 4.3 analog gain description registers [0x0080 to 0x0097] these registers are not dynamic but are required to be output on the status line so that it is possible to interp ret the meaning of the analog gain code(s). for a full description of the analog gain description registers, refer to section 6.5.1: analogue gain model on page 64 . table 11. analog gain description [0x0080 to 0x0093] index byte register name data type default type comment 0x0080 hi analogue_gain_capability 16ui 00.00 ro analogue gain capability 0 ? single global analogue gain only 0x0081 lo 0x0084 hi analogue_gain_code_min 16ui 00.00 ro minimum recommended analogue gain code that is, 0 (x1 gain) 0x0085 lo 0x0086 hi analogue_gain_code_max 16ui 00.f0 ro maximum recommended analogue gain code that is, 240 (x16 gain) 0x0087 lo 0x0088 hi analogue_gain_code_step 16ui 00.10 ro analogue gain code step size (1) 0x0089 lo 0x008a hi analogue_gain_type 16ui 00.00 ro analog gain type 0x008b lo 0x008c hi analogue_gain_m0 16si 00.00 ro analog gain m0 constant. m0 = 0 0x008d lo 0x008e hi analogue_gain_c0 16si 01.00 ro analog gain c0 constant. c0 = 256 0x008f lo 0x0090 hi analogue_gain_m1 16si ff.ff ro analog gain m1 constant. m1 =-1 0x0091 lo 0x0092 hi analogue_gain_c1 16si 01.00 ro analog gain c1 constant c1 = 256 0x0093 lo 1. for above gains of 0xe0, the step size is four. see figure 26 for gain values. this additional feature of the vx6953cb is outside of the smia specification. register map vx6953cb 32/107 8209023 rev 5 4.4 data format description registers [0x00c 0 to 0x00ff] the data format description registers specify which ccp csi-2 data formats the smia camera module supports. specifically vx6953cb supports raw 8, 10-8 compressed and raw10. 4.5 setup registers [0x0100 to 0x01ff] table 12. data format description registers [0x00c0 to 0x00ff] index byte register name data type default type comment 0x00c0 data_format_model_type 8ui 01 ro 2-byte generic data format model. always 0x01. 0x00c1 data_format_model_subtype 8ui 03 ro number of descriptors, that is, 3 0x00c2 hi data_format_descriptor_0 16ui 08.08 ro top 8-bits of internal pixel data transmitted as raw 8. 0x00c3 lo 0x00c4 hi data_format_descriptor_1 16ui 0a.0a ro top 10-bits of internal pixel data transmitted as raw 10. 0x00c5 lo 0x00c6 hi data_format_descriptor_2 16ui 0a.08 ro compress top 10-bits of internal pixel data to 8. transmitted as raw 8 mode. 0x00c7 lo table 13. setup registers [0x0100 to 0x01ff] index byte register name data type default type comment 0x0100 mode_select 8ui 00 rw mode select 0x00 - software standby 0x01 - streaming refer to section 3.3: device operating modes on page 18 . 0x0101 image_orientation 8ui 00 rw image orientation, that is, horizontal mirror and vertical flip. bit 0: 0 - no mirror, 1 - horizontal mirror enable bit 1: 0 - no flip, 1 - vertical flip enable 0x0103 software_reset 8ui 00 rw software reset. settin g this register to 1 resets the sensor to its power up defaults. the value of this bit is also reset. 0x00 - normal 0x01 - soft reset refer to section 3.3: device operating modes on page 18 8209023 rev 5 33/107 vx6953cb register map 0x0104 grouped_parameter_hold 8ui 00 rw the grouped parameter hold register disables the consumption of integration, gain and video timing parameters. 0x00 - consume parameters as normal 0x01 - hold parameters, do not consume values while set high refer to section 6.5.3: integration and gain parameter retiming on page 66 0x0105 mask_corrupted_frames 8ui 00 rw setting this register to 1 prevents the sensor outputing fr ames that have been corrupted by video timing parameter changes. 0x00 - normal 0x01 - mask corrupted frames 0x0110 csi_channel_identifier 8ui 00 rw the dma (ccp2) or virtual (csi2) channel identifier valid range for ccp2: 0 to 7 valid range for csi2: 0 to 3 0x0111 csi_signalling_mode 8ui 02 rw 0x00 - ccp2 data/clock signalling: 0x01 - ccp2 data/strobe signalling 0x02 - csi-2: this register should not be changed while the device is streaming data. 0x0112 hi csi_data_format 16ui 0a.0a rw the ms byte contains the bit width of the uncompresse d pixel data. the ls byte contains the bit width of the compressed pixel data. 0a.0a - raw10 mode 0a.08 - 10-8 compressed mode 08.08 - raw8 mode 0x0113 lo 0x0114 csi_lane_mode 8ui 00 rw number of data lanes in use. 00 - 1-lane 0x0120 gain_mode 8ui 00 ro 0x00 ? global analog gain. vx6953cb supports only global gain modes. 0x0136 hi extclk_frequency_mhz 16ur 06.00 rw 8.8 fixed point representation of the external clock frequency in mhz 0x0137 lo table 13. setup registers [0x0100 to 0x01ff] (continued) index byte register name data type default type comment register map vx6953cb 34/107 8209023 rev 5 4.6 integration time and gain registers [0x0 200 to 0x02ff] these registers are used to control the image exposure. see section 6.5: exposure and gain control on page 64 for more information. table 14. integration time and gain registers [0x0200 to 0x02ff] index byte register name data type default type comment 0x0200 hi fine_integration_time 16ui 02.54 rw fi ne integration time (pixels). 0x0201 lo 0x0202 hi coarse_integration_time 16ui 00.00 rw co arse integration time (lines). 0x0203 lo 0x0204 hi analogue_gain_code_global 16ui 00.00 rw global analog gain parameter (coded). see section 6.5.1: analogue gain model on page 64 for details of how to use this parameter. 0x0205 lo 0x020e hi digital_gain_greenr 16ur 01.00 rw gain code for greenr channel. 0x020f lo 0x0210 hi digital_gain_red 16ur 01.00 rw gain code for red channel. 0x0211 lo 0x0212 hi digital_gain_blue 16ur 01.00 rw gain code for blue channel. 0x0213 lo 0x0214 hi digital_gain_greenb 16ur 01.00 rw gain code for greenb channel. 0x0215 lo 8209023 rev 5 35/107 vx6953cb register map 4.7 video timing regi sters [0x0300 to 0x03ff] for a full description of the video timing registers please refer to chapter 6: video timing on page 51 . table 15. video timing registers [0x0300 to 0x03ff] index byte register name data type default type comment 0x0300 hi vt_pix_clk_div 16ui 00.0a rw number of system clocks per pixel clock. 0x0301 lo 0x0302 hi vt_sys_clk_div 16ui 00.01 rw s ystem clock divider value. 0x0303 lo 0x0304 hi pre_pll_clk_div 16ui 00.01 rw pre pll clock divider value. 0x0305 lo 0x0306 hi pll_multiplier 16ui 00.84 rw pll multiplier value. only even numbers should be used (odd values will result in the nearest lower even value being used). value: 132 0x0307 lo 0x0308 hi op_pix_clk_div 16ui 00.0a rw number of output system clocks per pixel clock. 0x0309 lo 0x030a hi op_sys_clk_div 16ui 00.01 rw output system clock divider value. 0x030b lo 0x0340 hi frame_length_lines 16ui 08.86 rw frame length. value: 2182 units: lines 0x0341 lo 0x0342 hi line_length_pck 16ui 0a.be rw line length. value: 2750 units: pixel clocks 0x0343 lo 0x0344 hi x_addr_start 16ui 00.00 rw x-address of the top left corner of the visible pixel data. units: pixels 0x0345 lo 0x0346 hi y_addr_start 16ui 00.00 rw y-address of the top left corner of the visible pixel data. (1) units: lines 0x0347 lo 0x0348 hi x_addr_end 16ui 0a.2f rw x-address of the bottom right corner of the visible pixel data. units: pixels 0x0349 lo 0x034a hi y_addr_end 16ui 07.a7 rw y-address of the bott om right corner of the visible pixel data. units: lines 0x034b lo 0x034c hi x_output_size 16ui 0a.30 rw width of image data output from the sensor module. units: pixels 0x034d lo register map vx6953cb 36/107 8209023 rev 5 4.8 image scaling regi sters [0x0400 to 0x04ff] 0x034e hi y_output_size 16ui 07.a8 rw height of image data output from the sensor module. units: lines 0x034f lo 0x0380 hi x_even_inc 16ui 00.01 rw increment for even pixels. x_even_inc must = 1 for focu s_estimation to operate effectively. units: pixels 0x0381 lo 0x0382 hi x_odd_inc 16ui 00.01 rw increment for odd pixels. units: pixels 0x0383 lo 0x0384 hi y_even_inc 16ui 00.01 rw increment for even pixels. y_even_inc must = 1 for focu s_estimation to operate effectively. units: pixels 0x0385 lo 0x0386 hi y_odd_inc 16ui 00.01 rw increment for odd pixels. units: pixels 0x0387 lo 1. has to be modulo 4 for correct operation of device. table 15. video timing registers [0x0300 to 0x03ff] (continued) index byte register name data type default type comment table 16. image scaling registers [0x0400 to 0x04ff] index byte register name data type default type comment 0x0400 hi scaling_mode 16ui 00.00 rw 0 ? no scaling 1 ? horizontal scaling 2 ? full scaling (horizontal and vertical) 0x0401 lo 0x0402 hi spatial_sampling 16ui 00.00 rw 0 ? bayer sampling 1 ? co-sited sampling 0x0403 lo 0x0404 hi scale_m 16ui 00.10 rw down scale factor m component (denominator) 0x0405 lo 0x0406 hi scale_n 16ui 00.10 ro down scale factor n component (numerator, always 16) 0x0407 lo 8209023 rev 5 37/107 vx6953cb register map 4.9 image compression re gisters [0x0500 to 0x05ff] 4.10 test pattern regi sters [0x0600 to 0x06ff] table 17. image compression registers [0x0500 to 0x05ff] index byte register name data type default type comment 0x0500 hi compression_mode 16ui 00.01 ro 1 ? dpcm/pcm compression (simple predictor) 0x0501 lo table 18. test pattern registers [0x0600 to 0x06ff] index byte register name data type default type comment 0x0600 hi test_pattern_mode 16ui 00.00 rw 0 ? normal operation (default) 1 ? solid color bars 2 ? 100% color bars 3 ? fade to grey? color bars 4 ? pn9 5 to 255 - reserved 0x0601 lo 0x0602 hi test_data_red 16ui 00.00 rw the test data used to replace red pixel data. range 0 to 1023. (1) 0x0603 lo 0x0604 hi test_data_greenr 16ui 00.00 rw the test data used to replace green pixel data on rows that also have red pixels. valid range 0 to 1023. (1) 0x0605 lo 0x0606 hi test_data_blue 16ui 00.00 rw the test data used to replace blue pixel data. range 0 to 1023. (1) 0x0607 lo 0x0608 hi test_data_greenb 16ui 00.00 rw the test data used to replace green pixel data on rows that also have blue pixels. range 0 to 1023. (1) 0x0609 lo 0x060a hi horizontal_cursor_width 16ui 00.00 rw defines the width of the horizontal cursor (in pixels). 0x060b lo 0x060c hi horizontal_cursor_position 16ui 00.00 rw defines the top edge of the horizontal cursor. 0x060d lo 0x060e hi vertical_cursor_width 16ui 00.00 rw defines the width of the vertical cursor (in pixels). 0x060f lo 0x0610 hi vertical_cursor_position 16ui 00.00 rw defines the left hand edge of the vertical cursor. a value of 0x0fff switches the vertical cursor into automatic mode where it automatically advances every frame. 0x0611 lo 1. some clipping of these values may occur to prevent false sync codes being generated register map vx6953cb 38/107 8209023 rev 5 4.11 fifo water ma rk [0x0700 to 0x0701] 4.12 dphy [0x0810 to 0x0811] 4.13 binning [0x0900 to 0x 0902] and [0x170c to 0x1719] table 19. fifo water mark registers [0x0700 to 0x0701] index byte register name data type default type comment 0x0700 hi fifo_water_mark_pixels 16ui 00.28 rw the level at which data starts to be transmitted out of the fifo (default is 40) 0x0701 lo table 20. dphy registers [0x0810 to 0x0811] index byte register name data type default type comment 0x0810 hi dphy_channel_mbps_for_ui 16ui 00.00 rw csi-2 dphy channel in mbps (10.4 fixed point). this is used by the dphy to calculate ui (unit interval) value. it does not control the sensor clock set-up, but should normally correspond to those settings. 0x0811 lo table 21. binning registers [0x0900 to 0x0902] index byte register name data type default type comment 0x0900 binning_mode 8ui 00 rw binning mode 0 - disable 1 - enable 0x0901 binning_type 8ui 00 rw high-nibble - column binning factor low-nibble - row binning factor 0x0902 binning_weighting 8ui 00 rw 1 - averaged 2 - bayer corrected 0x170c hi min_frame_length_lines_bin 16ui 00.28 r minimum frame length (lines) allowed in binning mode: 40 lines 0x170d lo 0x170e hi max_frame_length_lines_bin 16ui ff.ff r maximum frame length (lines) allowed in binning mode 0x170f lo 0x1710 hi min_line_length_pck_bin 16ui 0a.be r minimum line length (pixel clocks) allowed in binning mode 0x1711 lo 0x1712 hi max_line_length_pck_bin 16ui 03.ff r maximum possible number of pixel clocks per line in binning mode 0x1713 lo 0x1714 hi min_line_blanking_pck_bin 16ui 00.82 r minimum line blanking allowed in binning mode: 130 pixel clocks 0x1715 lo 8209023 rev 5 39/107 vx6953cb register map 4.14 shading correction [0x0b00] 4.15 defect correction [0x0b05 to 0x0b09] 0x1716 hi fine_integration_time_min_bi n 16ui 02.04 r minimum fine integration time allowed in binning mode (in pixels) 0x1717 lo 0x1718 hi fine_integration_time_max_m argin_bin 16ui 08.80 r margin used to determine the maximum fine integration time allowed in binning mode (in pixels) 0x1719 lo table 21. binning registers [0x0900 to 0x0902] (continued) index byte register name data type default type comment table 22. shading correction registers [0x0b00] index byte register name data type default type comment 0x0b00 shading_correction_enable 8ui 01 rw shading correction 0 - disable 1 - enable table 23. defect correction registers [0x0b05 to 0x0b09] index byte register name data type default type comment 0x0b05 mapped_couplet_correct_ena ble 8ui 01 rw mapped couplet correction 0 - disable 1 - enable 0x0b06 single_defect_correct_enable 8ui 01 rw single defect correction 0 - disable 1 - enable 0x0b07 single_defect_correct_weight 8ui 40 rw single defect correction weight 0x0b08 dynamic_couplet_correct_ena ble 8ui 00 rw dynamic couplet correction 0 - disable 1 - enable 0x0b09 dynamic_couplet_correct_wei ght 8ui 00 rw dynamic couplet correction weight register map vx6953cb 40/107 8209023 rev 5 4.16 edof [0x0b80 to 0x0b8a] 4.17 color feedback regist ers [0x0b8c to 0x0b95] table 24. edof registers [0x0b80 to 0x0b8a] index byte register name data type default type comment 0x0b80 edof_mode 8ui 00 rw edof control 0 - edof disabled (power saving) 1 - edof application (capture) 2 - edof estimation (preview) 0x0b81 edof_est_depth_of_field 8ui 00 ro not used in vx6953cb 0x0b82 edof_est_focus_distance 8ui 32 ro the estimated focus point (cm) 0x0b83 edof_sharpness 8ui 00 rw edof sharpness control 0x0b84 edof_denoising 8ui 00 rw edof denoising control 0x0b85 edof_module_specific 8ui 00 rw edof noise vs details control 0x0b88 hi edof_focus_distance 16ui 00.32 rw value supplied by the host which is used by vx6953cb for focus distance (in cm). 0x0000 to 0x7fff - manual mode 0x8000 to 0xffff - limited auto 0x0b89 lo 0x0b8a edof_estimation_control 8ui 00 rw edof estimator control 1 - uniform 2 - centre weight 4 - large spot 8 - narrow spot table 25. color feedback registers [0x0b8c to 0x0b95] index byte register name data type default type comment 0x0b8c hi colour_temperature 16sr 00.00 rw not supported by vx6953cb 0x0b8d lo 0x0b8e hi host_wb_stats_green_red 16ur 01.00 rw white balance gains to be applied by the host. these stats are used by the edof and the adaptive av to estimate the color temperature of the scene. 0x0b8f lo 0x0b90 hi host_wb_stats_red 16ur 01.00 rw 0x0b91 lo 0x0b92 hi host_wb_stats_blue 16ur 01.00 rw 0x0b93 lo 0x0b94 hi host_wb_stats_green_blue 16ur 01.00 rw 0x0b95 lo 8209023 rev 5 41/107 vx6953cb register map 4.18 integration time and gain pa rameter limit regi sters [0x1000 to 0x10ff] these registers are used to define exposure limits for the integrat ion control registers (0x200 to 0x203). see section 6.5: exposure and gain control on page 64 for more information. table 26. integration time and gain parameter limit registers [0x1000 to 0x10ff] index byte register name data type default type comment 0x1000 hi integration_time_capability 16ui 00.01 ro 0x0001 ? coarse and smooth (1 pixel) fine integration. 0x1001 lo 0x1004 hi coarse_integration_t ime_min 16ui 00.00 ro minimum coarse integration time. line periods. 0x1005 lo 0x1006 hi coarse_integr ation_time_max _margin 16ui 00.09 ro current frame length ? current max coarse exposure. line periods. 0x1007 lo 0x1008 hi fine_integration_tim e_min 16ui 02.54 ro minimum fine integration time. pixel periods. 0x1009 lo 0x100a hi fine_integratio n_time_max_ margin 16ui 03.be ro current line length ? current max fine exposure. pixel periods. 0x100b lo 0x1080 hi digital_gain_capability 16ui 00.01 ro 0x01 ? supports digital gain. 0x1081 lo 0x1084 hi digital_gain_min 16ur 00.08 ro 1/32 (0.03125) minimum 0x1085 lo 0x1086 hi digital_gain_max 16ur 01.f8 ro 1.96875 maximum 0x1087 lo 0x1088 hi digital_gain_step_size 16ur 00.08 ro 0.03125 step size 0x1089 lo register map vx6953cb 42/107 8209023 rev 5 4.19 video timing parameter limi t registers [0x1100 to 0x11ff] for a full description of the video timi ng parameter limit registers, refer to chapter 6: video timing on page 51 . table 27. video timing parameter limit registers [0x1100 to 0x11ff] index byte register name data type default type comment 0x1100 hi min_ext_clk_freq_mhz 32sf 40.c0 00.00 ro minimum external clock frequency units: mhz value: 6.0 0x1101 3rd 0x1102 2nd 0x1103 lo 0x1104 hi max_ext_clk_freq_mhz 32sf 41.d8 00.00 ro maximum external clock frequency units: mhz value: 27.0 0x1105 3rd 0x1106 2nd 0x1107 lo 0x1108 hi min_pre_pll_clk_div 16ui 00.01 ro minimum pre pll divider value value: 1 0x1109 lo 0x110a hi max_pre_pll_clk_div 16ui 00.04 ro maximum pre pll divider value value: 4 0x110b lo 0x110c hi min_pll_ip_freq_mhz 32sf 40.c0 00.00 ro minimum pll input clock frequency units: mhz value: 6.0 0x110d 3rd 0x110e 2nd 0x110f lo 0x1110 hi max_pll_ip_freq_mhz 32sf 41.40 00.00 ro maximum pll input clock frequency units: mhz value: 12.0 0x1111 3rd 0x1112 2nd 0x1113 lo 0x1114 hi min_pll_multiplier 16ui 00.25 ro minimum pll multiplier value: 37 0x1115 lo 0x1116 hi max_pll_multiplier 16ui 00.85 ro maximum pll multiplier value: 133 0x1117 lo 0x1118 hi min_pll_op_freq_mhz 32sf 43.e1 00.00 ro minimum pll output clock frequency units: mhz value: 450.0 0x1119 3rd 0x111a 2nd 0x111b lo 8209023 rev 5 43/107 vx6953cb register map 0x111c hi max_pll_op_freq_mhz 32sf 44.48 00.00 ro maximum pll output clock frequency units: mhz value: 800.0 0x111d 3rd 0x111e 2nd 0x111f lo 0x1120 hi min_vt_sys_clk_di v 16ui 00.01 ro minimum video-timing system clock divider value value: 1 in data/clock mode, the minimum value is 2. 0x1121 lo 0x1122 hi max_vt_sys_clk_div 16ui 00.04 ro maximum video-timing system clock divider value value: 4 0x1123 lo 0x1124 hi min_vt_sys_clk_freq_mhz 32sf 43.30 00.00 ro minimum video-timing system clock frequency units: mhz value: 176.0 0x1125 3rd 0x1126 2nd 0x1127 lo 0x1128 hi max_vt_sys_clk_freq_mhz 32sf 44.48 00.00 ro maximum video-timing system clock frequency units: mhz value: 800.0 0x1129 3rd 0x112a 2nd 0x112b lo 0x112c hi min_vt_pix_clk_freq_mhz 32sf 42.30 00.00 ro minimum video-timing pixel clock frequency units: mhz value: 44.0 0x112d 3rd 0x112e 2nd 0x112f lo 0x1130 hi max_vt_pix_clk_freq_mhz 32sf 42.b8 00.00 ro maximum video-timing pixel clock frequency units: mhz value: 92.0 0x1131 3rd 0x1132 2nd 0x1133 lo 0x1134 hi min_vt_pix_clk_div 16ui 00.04 ro minimum video-timing pixel clock divider value: 4 0x1135 lo 0x1136 hi max_vt_pix_clk_div 16ui 00.0a ro maximum video-timing pixel clock divider value: 10 0x1137 lo 0x1140 hi min_frame_length_lines 16ui 00.28 ro minimum frame length allowed. value = 40 units: lines 0x1141 lo table 27. video timing parameter limit registers [0x1100 to 0x11ff] (continued) index byte register name data type default type comment register map vx6953cb 44/107 8209023 rev 5 0x1142 hi max_frame_length_lines 16ui ff.ff ro maximum possible number of lines per frame. value = 65535 units: lines 0x1143 lo 0x1144 hi min_line_length_pck 16ui 0a.be ro minimum line length allowed. value = 2750 units: pixel clocks 0x1145 lo 0x1146 hi max_line_length_pck 16ui 3f.ff ro maximum possible number of pixel clocks per line. value = 16383 units: pixel clocks 0x1147 lo 0x1148 hi min_line_blanking_pck 16ui 00.82 ro minimum line blanking time in pixel clocks. value = 130 units: pixel clocks 0x1149 lo 0x114a hi min_frame_blanking_lines 16ui 00.22 ro minimum frame blanking in video lines is 34. 0x114b lo 0x1160 hi min_op_sys_clk_di v 16ui 00.01 ro minimum output system clock divider. value = 1 0x1161 lo 0x1162 hi max_op_sys_clk_div 16ui 00.68 ro maximum output system clock divider value = 104 0x1163 lo 0x1164 hi min_op_sys_clk_freq_mhz 32sf 40.8a 76.27 ro minimum output system clock frequency units: mhz value: 4.327 0x1165 0x1166 0x1167 lo 0x1168 hi max_op_sys_clk_freq_mhz 32sf 44.48 00.00 ro maximum output system clock frequency units: mhz value: 800.0 0x1169 0x116a 0x116b lo 0x116c hi min_op_pix_clk_div 16ui 00.08 ro minimum output pixel clock divider. value = 8 0x116d lo 0x116e hi max_op_pix_clk_div 16ui 00.0a ro maximum output pixel clock divider value = 10 0x116f lo 0x1170 hi min_op_pix_clk_freq_mhz 32sf 3e.dd 89.d9 ro minimum output pixel clock frequency units: mhz value: 0.433 (433 khz) 0x1171 0x1172 0x1173 lo table 27. video timing parameter limit registers [0x1100 to 0x11ff] (continued) index byte register name data type default type comment 8209023 rev 5 45/107 vx6953cb register map 0x1174 hi max_op_pix_clk_freq_mhz 32sf 42.b8 00.00 ro maximum output pixel clock frequency units: mhz value: 92.0 0x1175 0x1176 0x1177 lo 0x1180 hi x_addr_min 16ui 00.00 ro minimum x-address of the addressable pixel array value: always 0 0x1181 lo 0x1182 hi y_addr_min 16ui 00.00 ro minimum y-address of the addressable pixel array value: always 0 0x1183 lo 0x1184 hi x_addr_max 16ui 0a.2f ro maximum x-address of the addressable pixel array value = 2607 0x1185 lo 0x1186 hi y_addr_max 16ui 07.a7 ro maximum y-address of the addressable pixel array value = 1959 0x1187 lo 0x1188 hi min_x_output_size 16ui 01.00 ro minimum x output size in pixels. value: 256 0x1189 lo 0x118a hi min_y_output_size 16ui 00.04 ro minimum y output size in pixels. value: 4 0x118b lo 0x118c hi max_x_output_size 16ui 0a.30 ro maximum x output size in pixels. value: 2608 0x118d lo 0x118e hi max_y_output_size 16ui 07.a8 ro maximum y output size in pixels: value: 1960 0x118f lo 0x11c0 hi min_even_inc 16ui 00.01 ro minimum increment for even pixels 0x11c1 lo 0x11c2 hi max_even_inc 16ui 00.07 ro maximum increment for even pixels. even_inc must equal 1 for focus_estimation to operate effectively. 0x11c3 lo 0x11c4 hi min_odd_inc 16ui 00.01 ro minimum increment for odd pixels 0x11c5 lo 0x11c6 hi max_odd_inc 16ui 00.07 ro maximum increment for odd pixels 0x11c7 lo table 27. video timing parameter limit registers [0x1100 to 0x11ff] (continued) index byte register name data type default type comment register map vx6953cb 46/107 8209023 rev 5 4.20 image scaling parameter limit registers [0x1200 to 0x120b] 4.21 image compression paramete r registers [0x1 300 to 0x13ff] 4.22 csi lane mode capability [0x1600 to 0x1602] 4.23 binning capabilit y [0x1700 to 0x170b] table 28. image scaling parameter limit registers [0x1200 to 0x120b] index byte register name data type default type comment 0x1200 hi scaling_capablility 16ui 00.02 ro vx6953cb supports full (horizontal and vertical) scaling. 0x1201 lo table 29. image compression parameter limit registers [0x1300 to 0x13ff] index byte register name data type default type comment 0x1300 hi compression_capablility 16ui 00.01 ro vx6953cb supports dpcm/pcm compression 0x1301 lo table 30. csi lane mode capability registers [0x1600 - 0x1602] index byte register name data type default type comment 0x1600 ui_and_manual_dphy_ctrl_ca pability 8ui 00 ro csi2 dphy control capability ui enough 0x1601 csi_lane_capability 8ui 01 ro one csi-2 data lane supported 0x1602 csi_signallingmode_capability 8ui 07 ro number of data lanes available. bit[0]: 1 = ccp2 data/clock supported. 0 = not supported. bit[1]: 1 = ccp2 data/strobe supported. 0 = not supported. bit[2]: 1 = csi2 supported. 0 = not supported. table 31. binning capability registers [0x1700 to 0x170b] index byte register name data type default type comment 0x1700 binning_capability 8ui 01 ro vx6953cb supports binning 0x170b binning_weighting_capability 8ui 05 ro vx6953cb supports averaged and bayer corrected weighting 8209023 rev 5 47/107 vx6953cb register map 4.24 manufacturer specific re gisters - clipper 1 [0x31e8 to 0x31eb] by default, black level is 64. the end user ca n remove or modify it if needed to get the maximum output depth. table 32. manufacturer specific registers [0x31e8 to 0x31eb] index byte register name data type default type comment 0x31e8 enable 8ui 01 rw clipper 1 if set to 0: disabled if set to 1: enabled 0x31ea hi offset_req 16si 00.20 rw clipper offset request (signed bit) 0x31eb lo video data interface vx6953cb 48/107 8209023 rev 5 5 video data interface the video stream which is output from the vx6953cb through the compact camera port (ccp) or camera serial interface (csi) c ontains both video data and other auxiliary information. this chapter describes the frame formats. the vx6953cb is smia version 1.0 and mi pi csi-2 version 1.00 and d-phy v1.00 compliant meaning it is co mpatible with both v0.90 and v1.00 d-phy receivers. the selection of the video data forma t is controlled using the register csi_signalling_mode (0x0111): 0 - ccp2 data/clock 1 - ccp2 data/strobe 2 - csi-2 (default) changing the video data format must be performe d when the sensor is in software standby. the vx6953cb has one csi-2 data lane capable of transmitting at 800 mbps. however, while in ccp2 interface the maximum data rate is 640 mbps. the csi-2 data lane transmitter supports: ? unidirectional master ? hs-tx ? lp-tx (ulps) ? cil-muyn function the csi-2 clock lane transmitter supports: ? unidirectional master ? hs-tx ? lp-tx (ulps) ? cil-mcnn function 5.1 frame format the frame format for the vx6953cb is descri bed by the frame format descriptors, see table 10 on page 30 . for ccp this results in a frame as shown in figure 12 and for csi it results in a frame as shown in figure 13 . 8209023 rev 5 49/107 vx6953cb video data interface figure 12. vx6953cb ccp frame format figure 13. vx6953cb csi-2 frame format data format vx6953cb allows different data formats such as raw10, raw8 and 10-8 bit compressed: ? raw10 is a 10-bit depth raw bayer format ? raw8 is an 8-bit depth raw bayer format ? 10-8 is a 10-bit raw format compressed in 8-bit depth embedded data lines the embedded data lines provide a mechanism to embed non-image data such as sensor configuration details and image statistics values with a frame of data. vx6953cb has two embedded data lines at the start of the frame. dummy columns the vx6953cb has zero dummy columns. interline padding interframe padding bayer pixel data ccp embedded ls codes ccp embedded checksum codes ccp embedded le codes fe fs embedded data lines frame start code frame end code dummy columns bayer pixel data embedded data frame start packet frame end packet line blanking packet footer (pf) packet header (ph) frame blanking fe fs video data interface vx6953cb 50/107 8209023 rev 5 visible pixel data the visible pixels contain valid image data. t he correct integration time and analog gain for the visible pixels is specified in the embedde d data lines at the start of the frame. the number of visible pixels can be varied. black pixel data (zero integration time) the vx6953cb has zero black pixels. dark pixel data (light shielded pixels) the vx6953cb has zero dark pixels. manufacturer specific pixel data the vx6953cb has zero manufacturer specific pixels. interline padding/line blanking during interline padding all bits in the data stream in a ccp frame are set to 1. in a csi-2 frame there is no concept of line blanking being transmitted, the sensor will simply spend a longer time in the lp state between active line data. interframe padding/frame blanking during interframe padding all bits in the data stream in a ccp frame are set to 1. in a csi-2 frame there is no concept of fram e blanking being transmitt ed, the sensor will simply spend a longer time in the lp state at the end of the active data for a frame. 8209023 rev 5 51/107 vx6953cb video timing 6 video timing 6.1 output size the vx6953cb has the following methods available to achieve the required output size, these can be used independently or in conjunction with any other: ? programmable addressable region of the pixel array ? programmable width and height for output image data ? scaling ? subsampling the programmable image size and output si ze are independent functions. it is the responsibility of the ho st to ensure that these function s are programmed correctly for the intended application. these functions also redu ce the amount of data and therefore reduce the peak data rate of ccp2/csi-2. 6.1.1 programmable addressable region of the pixel array the native size for the vx6953cb is 2592 x 1944, the maximum addressable array is 2608 x 1960 which gives border pixels (outer eight rows and eight columns) for the color reconstruction algorithms to use at the edges of the array. by programming the x_addr_start, y_addr_start, x_addr_end and y_addr_end registers it is possible to use the full size of the array as yo u would do for a native size output or you can select a ?window of interest?. the addressed regi on of the array is used in any subsequent sub-sampling or scaling. see figure 14 . figure 14. programmable addressable region of the pixel array the host must ensure the following rules are kept; ? the end address must be greater than the start address ? the x and y start addresses are restricted to even numbers only, and the x and y end addresses are restricted to odd numbers only, to ensure that there is always a even number of pixels readout y_addr_max =1959 x_addr_max =2607 y_addr_min = 0 x_addr_min = 0 x_addr_max, y_addr_max x_addr_end, y_addr_end addressed pixel array region x_addr_start, y_addr_start x_addr_min, y_addr_min video timing vx6953cb 52/107 8209023 rev 5 6.1.2 programmable width and he ight for output image data the x_output_size and y_output_size registers are not intended as the primary cropping controls. they are intended to define the position of th e le/fe codes in the ccp data frame so that the sensor does not need to calculate this based on region of interest or sub-sampling settings. it should be expected that the host w ill set the output sizes to exactly enclose the output image data. if the host should not do this, the vx6953cb treats the output sizes as being calculated from the top left hand corner of the output array. so in the case where output sizes are smaller than the output data, the data is cropped from its right hand and lower limits. in the case where output sizes are larger than the output data, the lines shall be padded out to the defined output size with undefined data. figure 15. output size within a ccp data frame ccp2 requires that the number of pixels between the line start and the line end sync codes is: ? a multiple of 4 pixels for raw8 ? a multiple of 16 pixels for raw10 the host must control the x_output_size to ensure that the above criteria is met. 6.1.3 scaling the vx6953cb module is compliant with the ?profile level 2 - fu ll (horizontal and vertical)? level of image scaling. the image scaling function within the sensor module provides a flexible way of generating lower resolution full field of view image data, at a reduced data rates, for viewfinder and video applications. the scaler is able to scale the full resolution of the sensor module down to within 10% of a the target image size (the smallest output size is 256 x 192). this flexibility means that the vx6953cb module can support a wide range of lcd viewfinder sizes and different codec resolutions. the vx6953cb has three scaling modes which are controlled by the scaling_mode register shown in figure 16 . ccp output active line length interline padding interframe padding x_output_size y_output_size output data ccp embedded ls codes ccp embedded checksum codes ccp embedded le codes fe fs embedded data lines dummy columns 8209023 rev 5 53/107 vx6953cb video timing figure 16. scaling modes scaler quality the scaler supports two options for the spatial sampling of the scaled image data: (see figure 17 ): ? bayer sampled scaled image data the sampling point for the scaler for the output gr value appears to be in the centre of the gr pixel (i.e. between the 1 st and 2 nd pixels and between the 1 st and 2 nd rows of the original input bayer pixel data). the r (or b) sampling points are similarly in the centre of the r pixel (or b pixel). ? co-sited scaled image data the sampling point for the gr, r. gb and b vales in each output ?quad? are functions of the same colour input array pixels such that the spatial sampling point for all four appears to be in the centre of the ?quad? i.e. between the 2 nd and 3 rd pixels and between the 1 st and 2 nd rows. the spatial sampling mode is controlled by the spatial_sampling register. figure 17. scaler quality pixel array output scaling_mode register vx6953cb output 0- no scaling 1- horizontal scaling 2- full scaling (horizontal and vertical) pixel array output bayer samp led scaling co-sited sampling video timing vx6953cb 54/107 8209023 rev 5 down scaler factor the down scaler factor is controlled by an m/n ratio, scale_m is >= 16 and scale_n is fixed at 16. scale_m is in the range 16 to 164. this single down scale factor is used by both the horizontal and vertical scalers. the scaler acts upon the addressed region of the arra y which is determined by the x_addr_start, y_addr_start, x_addr_end and y_addr_end registers. figure 18. example image full scaled by a downscale factor of 2 6.1.4 subsampling subsampling is achieved by programming the x _odd_inc, y_odd_inc, x_even_inc and y_even_inc registers. if the pixel being readout has an even address then the address is incremented by the even increment value either x_even_inc or y_even_inc. if the pixel being readout has an odd address then the address is incremented by the odd increment value either x _odd_inc or y_odd_inc. the subsampled readout is disabled by sett ing the odd and even increment values to 1. subsampling acts upon the addressed region of the array which is determined by the x_addr_start, y_addr_start, x_addr_end and y_addr_end registers. for the edof focus estimation to operate ef fectively, the x_even_inc and y_even_inc registers must be 1. the equation for the subsamp ling factor is given below: down_scale_factor = scale_m scale_m scale_n 16 = downscale by 2 full (horizontal and vertical) scaling raw bayer image sub_sampling_factor even_inc odd_inc + 2 -------------------------------------------------- - = 8209023 rev 5 55/107 vx6953cb video timing figure 19. subsample readout example 6.1.5 binning the vx6953cb also has a binning mode that offe rs a reduced size full field of view image. the binning mode averages row and column pixel data. the binning mode results in a reduced number of lines and so can be used to give a higher image frame rate. compared to subsampling, binning makes use of the light gathered from the whole pixel array and it re sults in higher image quality. the binning mode will scale by 2 x 2 in the x and y directions. entering and exiting binning mode may or may not be performed when the sensor is in software standby. table 33 summarizes the register settings for ea ch of the binning mo des. refer to the personality file for further image quality settings. 8 5 6 7 g gr r b g gr r b g gr r b g gr r b g gr r b g gr r b g gr r b g gr r b g gr r b 4 1 2 3 9 10 8 567 4 123 9 010 0 111 33 3 1 1 1 3 3 3 example: x_even_inc=1 control range: min_even_inc=1 min_odd_inc=1 max_even_inc=7 max_odd_inc=7 x_odd_inc=3 y_even_inc=1 y_odd_inc=3 table 33. binning register settings register address normal (1) 1. min_fine_integration and max_fine_integration values for 2 x 2 subsampling modes are the same as normal (full resolution) mode. 2x2 binning_mode 0x0900 0 1 binning_type 0x0901 n/a 0x22 binning_weighting 0x0902 n/a 5 x_odd_inc 0x0383 1 3 y_odd_inc 0x0387 1 3 video timing vx6953cb 56/107 8209023 rev 5 binning repair binning can introduce some phases errors from the image perspective as it clusters the output of each color channel. gr,r,b and gb binned pixels are located around the same intersection point on the output lattice. to reduce this error, a binning ip is integrated into the imaging data path. the ip moves each binned color channel by 1/8 of an inter-pixel distance. therefore the top-left gr pixel moves into the top-left corner, the r pixel in the top-right moves in the top-right direction. this is shown in figure 20 . figure 20. binning repair 6.2 video timing this section specifies the timing for the image data that is readout from the pixel array and the output image data. these are not necessarily the same size. the application of all of the video timing read/w rite parameters must be retimed to the start of the frame boundary to ensure that the parameters are consistent within a frame. the video stream which is output from the vx 6953cb contains both video data and other auxiliary information. the vx6 953cb output coding conforms to the ccp raw8 and raw10 data format (see smia 1.0 part 2: ccp2 specification) including line checksums. reference smia 1.0 specification section 5 for a detailed description of video timing. 6.2.1 pll block the vx6953cb contains a phase locked loop (pll) block, which generates all the necessary internal clo cks from the external clock input. ch anges to the pll settings on the vx6953cb will only be consumed on the softwa re standby to str eaming mode transition. figure 21 shows the internal functional blocks, which define the relationship between the external input clock frequency and the pixel clock frequency. the majority of the logic withi n the device is clocked by vt_sys_clk however the cci block is clocked by the external input clock. image after binning ?displacement? vectors of the pixels image after phase shifts 8209023 rev 5 57/107 vx6953cb video timing figure 21. vx6953cb clock relationships 1. in order to comply with csi-2 d-phy specific ation, the op_sys_clk_freq_mhz minimum output frequency should be higher than 80 mhz. in order to comply with smia 1.0 part 2: ccp2 specification v1.0, the maximum op_sys_clk_freq_mhz for ccp2 is 640 mhz. the equations relating the input clock freq uency to pixel clock frequencies are: 6.2.2 spread spectrum clock generator the pll contains a spread spectrum clock generator (sscg) block for the purposes of emi reduction. this feature is off by default and is intended for use if channel blocking becomes an issue on the baseband platform. a primary source of emi is the high speed ccp serial data link. the modulation period and depth are fully programmable. the spread mode is selectable between center spread (default) or down spread. the sscg registers can only be reprogrammed with new values when the sensor is in software standby mode. min. 37 max. 133 pll_multiplier pre_pll_ clk_div range 1, 2, 4 ext. input clock external input clock ext_clk_freq_mhz pll input clock pll_ip_clk_freq_mhz pll output clock pll_op_clk_freq_mhz video timing pixel clock vt_pix_clk_freq_mhz video timing system clock vt_sys_clk_freq_mhz range 1, 2, 4 vt_sys_clk _div vt_pix_clk _div min. 4 max. 10 output timing system clock op_sys_clk_freq_mhz output timing pixel clock op_pix_clk_freq_mhz op_pixel _clk_div op_sys_ clk_div(1) min. 1 max. 66 range 8, 10 max 27mhz 6mhz min min min min min min min max max max max max max 800mhz 92mhz 44mhz 176mhz 0.433mhz 92mhz 800mhz 4.33mhz 450mhz 800mhz 6mhz 12mhz vt_pix_clk_freq_mhz ext_clk_freq_mhz pll_multiplier pre_pll_clk_div vt_sys_cl k_div vt_pix_clk_div ------------------------------------------------------------------------------------------------------------------------------- -- - = op_pix_clk_freq_mhz ext_clk_freq_mhz pll_multiplier pre_pll_clk_div op_sys_clk_div op_pix_clk_div ------------------------------------------------------------------------------------------------------------------------------- -------- = video timing vx6953cb 58/107 8209023 rev 5 6.2.3 framerate the framerate of the array readout and theref ore the output framerate is governed by the line length, frame length and the video timing pixel clock frequency. ? line length is specified as a number of pixel clocks, line_length_pck. ? frame length is specified as a numb er of lines, frame_length_lines. ? video timing pixel clock is specif ied in mhz, vt_pix_clk_freq_mhz. the equation relating the framerate to the line length, frame length and the video timing pixel clock frequency is: the maximum frame rate that can be achieved in profile 0 is 14.5 fps using csi-2 communication. table 34 provides examples of frame timing for raw10 mode for 14.5 fps for a variety of external clock frequencies. for csi-2 in order to achieve 15 fps it is necessary to use profile 2 to enable derating. table 35 provides examples of frame timing for raw10 for 15 fps for a variety of external clock frequencies. for ccp-2 in order to achieve 15 fps it is necessary to use 10-8 compressed data and profile 2 to enable derating. table 36 provides examples of frame timing for 10-8 compressed mode for 15 fps for a vari ety of external clock frequencies. table 34. external clock frequency examples - 5.0 mpixel raw10 14.5 fps (csi-2) ext clk freq pre-pll clk div pll multiplier vt sys clk div vt pixel clk div vt pixel clock op sys clk div op pixel clk div op pixel clock line length frame length mhz integer integer (dec) integer integer mhz integer integer mhz pixel clks lines (dec) 9.60 1 83 1 10 79.68 1 10 79.68 2750 1996 12.00 2 133 1 10 79.80 1 10 79.80 2750 1996 13.00 2 123 1 10 79.95 1 10 79.95 2750 1996 table 35. external clock frequency exam ples - 5.0 mpixel raw10 15 fps (csi-2) ext clk freq pre-pll clk div pll multiplier vt sys clk div vt pixel clk div vt pixel clock op sys clk div op pixel clk div op pixel clock line length (1) 1. the min_line_length_blanking = 356ns + 88*ui for csi-2. frame length mhz integer integer (dec) integer integer mhz integer integer mhz pixel clks lines (dec) 9.60 1 83 1 9 88.5 1 10 79.68 2950 2000 12.00 2 133 1 9 86.67 1 10 79.80 2950 2003 13.00 2 123 1 9 88.83 1 10 79.95 2950 2007 framerate vt_pix_clk_freq_mhz line_length_pck frame_length_lines --------------------------------------------------------------------------------------------------- = 8209023 rev 5 59/107 vx6953cb video timing csi-2 maximum output frame rate in 5 mpixel image using 10-8 compression can be an option for the end user to increase the frame rate and keep a high quality image. there is no visibl e loss in using 10-8 compressed data format over raw10 format. 1080p30 hd video format in order to achieve 1080p30, it is necessary to use csi2 mode with raw8 or 10-8 compressed data and profile 2 to enable derating. table 38 provides examples of frame timing for 1080p30. table 36. external clock frequency exam ples - 5.0 mpixel 10-8 compressed 15 fps ext clk freq pre-pll clk div pll multiplier vt sys clk div vt pixel clk div vt pixel clock op sys clk div op pixel clk div op pixel clock line length frame length mhz integer integer (dec) integer integer mhz integer integer mhz pixel clks lines (dec) 9.60 1 66 1 7 90.5 1 8 79.2 3027 1996 12.00 2 106 1 7 90.9 1 8 79.5 3027 2002 13.00 2 98 1 7 91 1 8 79.63 3027 2004 table 37. example - 5.0 mpixel 10-8 compressed 16.65 fps (csi-2) ext clk freq pre-pll clk div pll multiplier vt sys clk div vt pixel clk div vt pixel clock op sys clk div op pixel clk div op pixel clock line length frame length mhz integer integer (dec) integer integer mhz integer integer mhz pixel clks lines (dec) 12.00 2 122 1 8 91.5 1 8 91.5 2750 1998 24.00 4 122 1 8 91.5 1 8 91.5 2750 1998 table 38. external clock frequency examples - 1080x1920 in 10-8 bit @ 30fps (ccp) ext clk freq pre-pll clk div pll multiplier vt sys clk div vt pixel clk div vt pixel clock op sys clk div op pixel clk div op pixel clock line length frame length mhz integer integer (dec) integer integer mhz integer integer mhz pixel clks lines (dec) 12.00 2 122 1 8 91.5 1 8 91.5 2750 1108 24.00 4 122 1 8 91.5 1 8 91.5 2750 1108 video timing vx6953cb 60/107 8209023 rev 5 720p30 video format in order to achieve 720p30, either ccp2 or csi2 can be used in profile 2 to enable derating. table 39 provides examples of frame timing for 720p30. 6.2.4 derating to provide a wide range of data rate reduction options the full image scaler is able to reduce the data and therefore data rates in both t he horizontal and vertical directions. in the vx6953cb this is achieved by the use of a fifo between video timing and output clock domains. it is therefore necessary for the host to confi gure the op clock domain to ensure that the fifo neither overfl ows or underflows figure 22. timing block diagram derating shows the difference between the video timing domain and the output clock domain. table 39. 720x1280 @ 30 fps in raw10 (csi2/ccp2) ext clk freq pre-pll clk div pll multiplier vt sys clk div vt pixel clk div vt pixel clock op sys clk div op pixel clk div op pixel clock line length frame length mhz integer integer (dec) integer integer mhz integer integer mhz pixel clks lines (dec) 12.00 2 106 1 10 63.6 1 10 63.6 2750 770 pixel array scaler fifo tx logic output clock domain video timing clock domain pre-pll clock divider pll multiplier vt sys clock divider vt pixel clock divider op sys clock divider op pixel clock divider derating = vt_sys_clk_div * op_pix_clk_div op_sys_clk_div * vt_pix_clk_div 8209023 rev 5 61/107 vx6953cb video timing fifo the fifo is used to implement the data rate reduction required for profile 1 and 2 operation. the concept of an output frame length and a line length for the output timing domain does not exist for smia devices such as the vx6953cb. this is a result of the fifo input data patterns being different depending on scaling factor and if the data is co-sited or bayer sampled, which results in vari able interframe and interline blanking time between lines and between frames. figure 23. smia output timing when the fifo reaches a certain level of usage the ccp transmitter starts outputting a line containing x_output_size pixels . this then naturally tracks any variation in the input data rate, if the water mark is set co rrectly underflow is not possible. figure 24. fifo water mark control if the derating factor >= downscale factor then the average input rate of a burst of a line of scaler output data into the fifo is always faster than the output data rate, in this case the fifo_water_mark_pixels can be set to eight as th e fifo input data rate is always faster than the fifo output data rate. if the derating factor < downscale factor then the average input rate of a burst of a line of scaler output data into the fifo is slower than the output data rate, in this case the fifo_water_mark_pixels must be set to avoid underflow. output data: 2608 pixels x 1960 lines output line length (does not exist in smia) output frame length (does not exist in smia) ccp active video line blanking cs le fifo water mark level = ccp output trigger fifo usage ls ls le cs data data x_output_size + additional_cols x_output_size + additional_cols video timing vx6953cb 62/107 8209023 rev 5 calculate the floating point value of the fifo_water_mark_pixels: then round up this value; 6.3 bayer pattern the three color (red, green, blue) filters are arranged over the pixel array in a repeated 2 x 2 arrangement known as the bayer pattern. when the sensor array is read, the output order of red, green, blue depends on the settings of vertical flip and horizontal mirror. see figure 25 for read-out order for the default settings of vertical flip and horizontal mirror both turned off. vertical flip will change the fi rst line to be output from a green/red line to a blue/green line and horizontal mirror will change the sequence wit hin a line, sa y, green/red to red/green. as shown in figure 25 , the first pixel to be readout fr om the imaging array will be green followed by red. * scale_factor scale_factor - derating x_output_size fifo_water_mark_pixels(flt)= fifo_water_mark_pixels = fifo_water_mark_pixels(flt) + 40 8209023 rev 5 63/107 vx6953cb video timing figure 25. bayer pattern blue green green red blue green green red 3 2 1 0 1 3 2 0 5 4 blue green green red 5 4 7 6 2603 2602 2601 2600 1955 1957 1956 1954 2605 2604 1959 1958 2607 2606 blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red 1960 active rows video timing vx6953cb 64/107 8209023 rev 5 6.4 image compression the objective of the image compression is to reduce the required bandwidth in transmission between the sensor and the host. the key features of the dpcm/pcm compression algorithm are: ? visually lossless ? low cost implementation (no line memories are required) ? fixed rate compression the 10-bit to 8-bit dpcm/pcm image compression algorithm is supported by vx6953cb. 10-bit to 8-bit compression has the additional advantage that one pixel value equals 1 byte of data. the level of compression is controlled thro ugh the csi_data_format register. the same register is also used to enable and disable compression. the compression_mode register is used to sele ct the compression algorithm. currently only the dpcm/pcm technique is supported. therefor e the value of this register is always 0x01. the compression_capability regist er tells the host whether a s ensor module does or does not have compression and, if it has compressio n, what is the compre ssion technique. again currently only the dpcm/pcm technique is supported. please also refer to section 10 of the smia1.0 specif ication document. 6.5 exposure and gain control vx6953cb does not contain any form of automatic exposure control. to produce a correctly exposed image the integration period and analogue gain for the pixels must be calculated by an exposure control algorithm implemented externally. the parameters are the written to the vx6953cb using the cci interface. the exposure control parameters available on vx6953cb are: ? fine integration time ? coarse integration time ? analog gain ? digital gain the exposure control parameter registers are defined in chapter 4 on page 29 . integration time and analogue gain capability registers should be used to determine the exposure control parameter limits for a given video timing configuration. see section 6.7 of the smia 1.0 part 1 specification for more info rmation on how to interpret the integration and gain capability registers and how to calculate exposure and gain limits. 6.5.1 analogue gain model vx6953cb only supports the single global analog gain mode. vx6953cb has a 16-bit register (0x0204 and 0x0205) to control analog gain. however, only 4 bits are supported by the smia1.0 description. two extra bits can be used for fine gain between values 8 and 16 but their description is not currently supported by smia1.0 specification. figure 26 shows how the analog gain bits are used for vx6953cb. use only coarse gain bits for standard 1/x functionality. 8209023 rev 5 65/107 vx6953cb video timing figure 26. analogue gain register format the following generic equation describes vx6953 cb coarse gain behavior specified by the analog gain description registers 0x008a - 0x0093: where: ? m1 = -1 ? c0 = 256 ? c1 = 256 table 40 specifies the valid analog gain values for vx6953cb. also refer to section 6.3 of the smia1.0 specification document. table 40. analog gain control gain value (0x0204/0x0205) coarse gain code [a7:a4] coarse analog gain fine gain code [a3:a2] fine analog gain 0x0000 0000 0.0 db (x1.00) 00 n/a 0x0010 0001 0.6 db (x 1.07) 00 n/a 0x0020 0010 1.2 db (x1.1) 00 n/a 0x0030 0011 1.8 db (x1.2) 00 n/a 0x0040 0100 2.5 db (x1.3) 00 n/a 0x0050 0101 3.3 db (x1.5) 00 n/a 0x0060 0110 4.1 db (x1.6) 00 n/a 0x0070 0111 5.0 db (x1.8) 00 n/a 0x0080 1000 6.0 db(x2.0) 00 n/a 0x0090 1001 7.2 db (x2.3) 00 n/a 0x00a0 1010 8.5 db (x2.7) 00 n/a 0x00b0 1011 10.1 db (x3.2) 00 n/a 0x00c0 1100 12.0 db (x4.0) 00 n/a 0x00d0 1101 14.5 db (x5.3) 00 n/a 0x00e0 1110 18.1 db (x8.0) 00 n/a 0x00e4 1110 fine ctrl 01 19.2 db (x9.1) 0x00e8 1110 fine ctrl 10 20.6 db (x10.7) 0x00ec 1110 fine ctrl 11 22.1 db (x12.8) 0x00f0 1111 24.1 db (x16.0) 00 n/a a7 a6 a5 a4 a3 a1 a0 a8 a9 a15 a14 a13 a12 a11 a10 a2 coarse gain fine gain not used not used gain c0 m ( 1x ? ? c1 ) + = video timing vx6953cb 66/107 8209023 rev 5 6.5.2 digital gain to help compensate for the relatively coarse analog gain steps, vx6953cb contains a digital multiplier to ?fill? in the missing steps. by mixing analog and digital gain it is possible to implement 3% gain steps acro ss the full 1x to 16x gain range. the details of the digital gain implementation are: ? four individual 16-bit digital channel gains - one per bayer channel ? digital_gain_greenr (0x020e and 0x020f) ? digital_gain_red (0x0210 and 0x0211) ? digital_gain_blue (0x0212 and 0x0213) ? digital_gain_greenb (0x0214 and 0x0215) ? the digital gain range for each channel is 1.000 to 1.96875 in steps of 0.03125 (1/32) that is, five fractional bits ? digital_gain_min {0x1084:0x1085} = 0x0100 (1.00) ? digital_gain_max {0x1086:0x1087} = 0x01f8 (1.96875) ? digital_gain_step {0x1088:0x1089} = 0x0008 (0.03125) 6.5.3 integration and gain parameter retiming the modification of exposure parameter (coarse, fine, clock division or gain) register values does not take effect immediately. the exact time at which changes to certain pa rameters take effect is controlled both to ensure that each frame of image data produced has consistent settings and that changes in groups of related parameters can be synchronized. a group of parameter changes is marked by the host using a dedicated boolean control parameter, grouped_parameter_hold (register 0x0104). any changes made to ?retimed? parameters while the groupe d_parameter_hold si gnal is in the ?hold? state will be considered part of the same group. only when the grouped_parameter_hold control signal is moved back to the defaul t ?no-hold? state will the grou p of changes be executed. 8209023 rev 5 67/107 vx6953cb application 7 application 7.1 schematics figure 27. example of a mobi le camera application (ccp2) note: ccp 100r termination may be internal to a sublvds receiver (for example, stv0986/stv0987). note: no external supply decoupling capacitors are required as the necessary components are integrated into the module. note: if the master cci bu s is powered to voltage > vdig+0.5v, it is mand atory to insert a level shifter on the sensor scl and sda lines to prevent from any electrical damage. note: extclk has a s chmitt trigger input. vx6953cb 1.8v extclk data+ clk- gnd scl sda 1.8v external clock power down signal 100r 100r 4.7k xshutdown data- clk+ sublvds data sublvds clock cci control lines vdig vcap . 2.8v vana . vcap . application vx6953cb 68/107 8209023 rev 5 figure 28. example of a mobi le camera application (csi2) note: the csi-2 receiver is mandated to have an internal terminatio n which is dynamically switched in and out depending on whether the link is in high speed mode or in low power mode. this transition happens every line. 7.2 personality file and firmware updates contact st for the latest copy of the sensor ?s tartup procedure application note? that details the procedure to initialize the sensor prior to streaming. it includes fw and sensor optimization settings. the settings must be wr itten through the cci link to overwrite the default register settings, see chapter 4: register map on page 29 . vx6953cb 1.8v extclk data+ clk- gnd scl sda 1.8v external clock power down signal 4.7k xshutdown data- clk+ sublvds data sublvds clock cci control lines vdig vcap . 2.8v vana . vcap . 8209023 rev 5 69/107 vx6953cb edof control 8 edof control the vx6953cb module uses a fixed focused le ns with optical aberrations that the edof reconstruction engine is designed for so as to recover the resolution and increase the depth of field in the range of 15 cm to infinity. t he focus is tuned for far distances > 2m but for closer distances where a standard fixed focus camera would show a blur image, the edof correction is capable of recovering significantly the resolution. figure 29. what is sharp? some optics facts: ? the depth of focus narrows with reduction in object distance or with aperture increase. ? if the lens is focussed at the hyper-focal distance, the sharpness will be the same from hyperfocal/2 to infinity. ? the depth of field is defined by the range of scene distances that appears acceptably sharp in the image. ? the size of a pixel (1.4um) can be defined as a blurred spot. a blurred spot smaller than 1.4um is registered as sharp. above that va lue the spot will look blurred (refer to circle of confusion graph). considering the above points, edof aims to make the blur spot invariant (or change its reference) over a range of objects distances, thus defeating the obvious geometric optical effects to enhance the depth of field. edof control vx6953cb 70/107 8209023 rev 5 the plot in figure 30 shows the edof main principle: figure 30. edof main principle 8.1 edof capabilities the edof reconstruction engine is applied to the image after defect correction. it has denoising, sharpening, deconvolution algorith ms among others that allow recovering the resolution. the end user should not use the edof ip as a sharpness block. edof has a depth of field recovery role. oversharpening the image using edof before the host image processing might alter the final image quality. the edof reconstruction engine can improve the depth of field for a coloured image in the range of 30 cm to infinity and for a monochrome image below 30 cm. the edof block works with ranges of distan ces for which the corr ection applied will be different: ? 5 mpixel edof camera: ? super macro mode: < 30cm ? macro mode: 30cm to 59cm ? portrait: 60cm to 249cm ? landscape: 250cm to infinity the distance estimation analyzes gradients and relative sharpness among channels. it first returns a measure of the sharpest chann el in the image giving a macro ?vote? when the sharpest channel is the blue one, portrait when it?s the green and landscape when it?s the red. the relative sharpness among channel varies with the object distance but also in the field of the image (field curvature), so the votes are then weighted by calibration data in order to obtain the most appropriate mode or distance at the output. note: the aim of the distance estimation is not to obtain a precise distance but to select the best parameterization for the correction to be applied in capture, therefore the returned distance or specified distances range is indicative only. 8209023 rev 5 71/107 vx6953cb edof control like an auto-focus module: ? the algorithm has failure cases, but the corr ection is constrained in order to always have acceptable image quality even if not optimal. ? for a single image several modes are often possible and giving same level of image quality. for overlap distances (between macro and portrait modes, or between portrait and landscape modes), two of the channels may have the same level of sharpness, so any of the two corresponding distances could be returned, depending on scene content and field curvature of the module. for scenes with objects at different distances, any of the three distances could be returned depending on content of the sc ene, field curvature of the module and spatial weights used for estimation (edof_estimation_control). supermacro mode is used for bar code and business card reading. supermacro mode uses a monochrome image. below 30cm distance, the mtf is lost and there is too little green and red pixel information to build a colored image. however, the blue pixel has enough mtf to reconstruct a monochrome image. 8.2 control interface vx6953 has a 100 khz/400 khz i 2 c compatible 2-wire control in terface. it uses the smia 16-bit index, 8-bit data message format. the cci interfaces allows the programming of the edof control register. 8.3 edof control registe rs [0x0b80 to 0x0b8a] table 41. edof registers [0x0b80 to 0x0b8a] index byte register name data type default type comment 0x0b80 edof_mode 8ui 00 rw edof control 0 - edof disabled (power saving) 1 - edof application (capture) 2 - edof estimation (preview) 0x0b82 edof_est_focus_distance 8ui 32 ro the estimated focus point (cm) 0x0b83 edof_sharpness 8ui 00 rw edof sharpness control 0x7f: manual mode 0x80 to 0xff: automatic mode 0x0b84 edof_denoising 8ui 00 rw edof denoising control 0x0b85 edof_module_specific 8ui 00 r w edof noise vs details control edof control vx6953cb 72/107 8209023 rev 5 8.3.1 edof_mode (0xb80) the edof block can be disabled or enabled. the in terest of disabling this block would be to save some power consumption. when enabled, edof has two modes: ? estimation mode this mode is dedicated to image preview (v iewfinder) only. edof correction is not applied but statistics are gathered for dist ance estimation. estimation mode can be full resolution, subsampled or binned image up to a maximum of x4 in both directions. if too much subsampling is performed the image out of the sensor becomes sharp and focus distance estimation is not possible. this is similar to the me chanical auto focus control which requires an image large enough to allow detecting sharpness variation with focus. isp should therefore ensure that at least the last frame before capture is set to either one quarter of the full resolution in each direction or a higher resolution. in other words, as an exampl e, this means that the minimum input image size when no crop is applied on the sensor is approximately 640 x 480 for a 5 mpixel sensor. ? application mode this mode is for capture (or snapshot) mode. the edof distance calculated during estimation is applied to the image. the app lication mode can only be enabled after the estimation mode has been selected, otherwise the edof correction will not be applied. edof cannot be applied to subsampled or binned images as it is not necessary to correct images when they are subsampled as the image blur introduced by the lens does not need to be corrected when images are downscaled. no focus distance estimates are performed in application mode, even in multi-shot mode. for preview mode, set the 0x0b80 register in estimation mode: 0x0b80 = 0x02; // edof enabled for estimation mode for capture mode, set the 0x0b80 register in application mode: 0x0b80 = 0x01; // edof enabled for application mode note: before enabling application mode, estimation mo de has to be applied for a minimum of one frame so as to estimate the edof focus distance. this information is used in application mode when the image data is corrected. if estimation mode is not enabled prior to application mode, no correction will be applied to th e captured image. 0x0b88 hi edof_focus_distance 16ui 00.32 rw value supplied by the host which is used by vx6953cb for focus distance (in cm). 0x0000 to 0x7fff - manual mode 0x8000 to 0xffff - limited auto 0x0b89 lo 0x0b8a edof_estimation_control 8ui 00 rw edof estimator control 1 - uniform 2 - centre weight 4 - large spot 8 - narrow spot table 41. edof registers [0x0b80 to 0x0b8a] (continued) index byte register name data type default type comment 8209023 rev 5 73/107 vx6953cb edof control 8.3.2 edof_est_focus_distance (0x0b82) the edof_est_focus_distance register ( 0x0b82) is read only. this register tells the user the estimated focus point that the edof function ha s calculated. register values for a 5 mpixel edof camera are: ? macro mode: 0x1e ? portrait: 0x3f ? landscape: 0xfa 8.3.3 edof tuning sl iders (0xb83 to 0x0b85) the three key registers for the end user tuning are the sharpness, denoising and noise versus detail registers. recommended settings for the recommended settings of the edof sliders (0x0b83 to 0x0b85) refer to the relevant personality file, see section 7.2 on page 68 . note: upon request, st can provide the edof application note that gives details for host tuning. 8.3.4 edof focus distance (0x0b88) for automatic mode, the value range is 0x8000 to 0xffff. whatever value is selected within this range will enable automatic distan ce estimation. st re commends setting the edof estimation mode to automatic mode. in this mode, when the user selects capture mode, the edof processi ng will automatically use the last estimate of the focus distance obtained in preview mode. note: if it is necessary to switch between estimation mode and application mode while in software standby, then a patch must be loaded to enable this feature. if the patch is not loaded, switching must be performed wh ilst streaming. otherwise the host must read the estimation data (from register 0x0b82) immediately before going to software standby and rewrite that data (to register 0x0b88) before re starting streaming in application mode. for manual mode, the value to be set in the register is the value of the distance in cm. the range is 0x0000 to 0x7fff. if you want to go to one of the following modes, apply the specified value for a 5 mpixel edof camera: ? super macro mode: 0 to 29cm ? macro mode: 30 to 59cm ? portrait: 60 to 249cm ? landscape: 250 to 32767cm supermacro mode only works in manual mode. refer to section 8.4: supermacro mode for more detailed information. edof control vx6953cb 74/107 8209023 rev 5 8.3.5 edof estimati on control (0x0b8a) this register selects the region of interest (r oi) on which to apply the distance estimation processing. four different rois are available: ? 0 or 1: uniform ? 2: center-weighted ? 4: spot (large) ? 8: spot (narrow) considering the above order, with increasing values, the esti mation will increase focus on objects in the centre of the image. figure 31. focus strategy weightings 8.4 supermacro mode unlike the other modes (macro, portrait and landscape), supermacro mode cannot be managed by the automated distance range estimato r. the reason is that at distances below 30cm, there is very little info rmation in green and red channel s though there is a significant energy in the blue channel. the distance esti mator needs the four color channel information to estimate the distan ce. below 30cm, unless the distance is manually programmed using register 0x0b88, the edof co rrection will not be accurate. for text or bar code reading, a monochromatic image can be used. edof supermacro mode can be used for that purpose as the edof reco nstruction engine would use the blue channel information to calculate the suitable sharpness and denoising. to enable supermacro mode, the user has to manually program the register 0x0b88 to set a value for distances below 30cm. the register value being the value of the distance in cm. narrow spot large spot center 32 2 2 2 2 2 22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 0 1 0 0 00 0 0 0 0 0 0 0 00 00 0 1 1 1 1 1 1 1 1 uniform 1 1 1 1 1 11 11 1 11 1 11 11 1 1 1 11 1 11 the image is arranged as 5x5 regions for the weightings. 8209023 rev 5 75/107 vx6953cb edof control 8.5 video modes and edof setting a video mode implies targetting a reducti on in the image size and an increase of the frame rate. the st 5 mpixel cameras are smia profile 2 compliant therefore output images can be downscaled in both x and y dimensions either using a digital scaling post edof engine or by subsampling pixels before the edof engine. downsampling or binning by a factor of two or more in each direction increases the sharpness enough to remove the need to process the raw image. therefore image processing is disabled in preview mode within the edof processor in order to save power and the image is simply copied on the outpu t. the consequence is that the image must be subsampled by a factor of 2x2 at least to get distance information and a usable raw image. to summarize, it is recommended that edof is forced to landscape mode when in video: ? if subsampling or binning is used and outp ut image is at least full size image/4 ? if a scaling+cropping method is used from a full size image to output a smaller image and output image < (2*full size image)/3 ? for a crop of a full resolution image 8.6 edof and white balance the edof reconstruction engine requires the white balance gains to be programmed by the host (by i2c writes) frame after frame to the colour feedback register (0x0b8e-0x0b95) of the sensor. these white balance gains must be corresponding the wb output ones to prevent from fringing artefacts. these gains are also used for the sensor adaptive lens shading correction if enabled. the white balance gains are required in both preview and capture modes. the four host white balance gains to be programmed are listed in table 42 . table 42. color feedback registers [0x0b8c to 0x0b95] index byte register name data type default type comment 0x0b8c hi colour_temperature 16sr 00.00 rw not supported by vx6953cb 0x0b8d lo 0x0b8e hi host_wb_stats_green_red 16ur 01.00 rw white balance gains to be applied by the host. these stats are used by the edof and the adaptive av to estimate the color temperature of the scene. 0x0b8f lo 0x0b90 hi host_wb_stats_red 16ur 01.00 rw 0x0b91 lo 0x0b92 hi host_wb_stats_blue 16ur 01.00 rw 0x0b93 lo 0x0b94 hi host_wb_stats_green_blue 16ur 01.00 rw 0x0b95 lo edof control vx6953cb 76/107 8209023 rev 5 as a preliminary correlation exercise between st, the end user and the edof engine provider, we recommend that the end user verifi es that the white balance gains calculated by the host auto-white balance processing engine for a 18% grey chart unde r d65 illuminant at 1000 lux are equal to the following values (normalized on green channels): ? green channels gain = 1 (normalized gain) ? red channel gain = 1.5 ? blue channel gain = 1.12 8209023 rev 5 77/107 vx6953cb image optimization 9 image optimization the sensor has the following image optimizations: ? mapped couplet correction (using couplet location stored in nvm memory) ? dynamic couplet and singlet correction ? green imbalance correction ? depth of field correction (edof) ? lens shadin g correction figure 32 shows the processing pipe. figure 32. processing pipe note: defect correction must be enabled as it occurs before the edof processing. defect correction settings are given in the personality file (parameters to be loaded during sensor initialisation), see section 7.2 on page 68 . lens shading correction mapped couplet correction edof green imbalance correction imaging array dynamic couplet and singlet correction image optimization vx6953cb 78/107 8209023 rev 5 9.1 defect categorization 9.1.1 pixel defects illuminated defects are tested wit h a flat field illumination and a pass-fail criteria that is a percentage deviation from a local mean. in order to effectively test the sensor in a reasonable test time, it is necessary to put the limits of gain error above the normal noise distribution of photon shot no ise and sensor noise otherwise false single pixel fails are detected. a typical defect criteria for single-pixel gain errors is 9%. in fact, any element in the array outside 9% is a ?minor? fail, and outside of 25% is a ?major? fail. note: the defect detection method is applied to raw bayer images. 9.1.2 sensor arr ay area definition for specific aspects of pixel defect testing th e image sensor array is subdivided into two regions as illustrated in figure 33 . figure 33. vx6953cb pixel defect test area the inner array in figure 33 is centre justified, in the x an d y axis, with respect to the outer array. the inner array is 50% of the full width and 50% of the full height of the larger outer array, therefore the inner array is one quarter of the area of the outer array. note: the border pixels (outer eight rows and columns) affect the image quality of the reconstructed picture to a lesser degree than the actual image pixels (2592 x 1944), due to their lower contribution within th e reconstruction algorithm, but for simplicity we test them as the image pixels, hence t he test image size for defects will be 2608 x 1960. outer area inner area 1304 pixels 2608 pixels 1960 pixels 980 pixels 8209023 rev 5 79/107 vx6953cb image optimization 9.1.3 pixel fault numbering convention the pixel notation is shown in figure 34 . for the purposes of the test the 3 x 3 array describes nine bayer pixels of a common color, that is, all the pixels will either be red, green (a) or blue. the pixel under test is x . if a pixel under test is on the edge, the array is reduced to its existing neighbor pixels (that is, the first pixel uses only a 2 x 2 array). figure 34. pixel numbering notation 9.1.4 single pixel faults stmicroelectronics defines a si ngle pixel fail as a failing pixe l with no adjacent failing same color neighbors. a single pixel fail can be: ? ?stuck at white? where the output of the pixe l is permanently saturated regardless of the level of incident light and exposure level ? ?stuck at black? where the pixel output is ze ro regardless of the level of incident light and exposure level (major fail) or simply a pixel that differs from it?s immediate neighbors by more than the test threshold (minor fail). in the example in figure 35 , the pixel x is a fail. for this pixel to be a single pixel fail the pixels at positions [0], [1], [2], [3], [4], [5], [6] and [7] must be ?good? pixels that pass final test. the implemented te st program will pass a sensor with up to the defined limit of single pixel faults per color channel. defect correction algorithms will correct the pixel faults in the final image. figure 35. single pixel fault a. the green pixels are split over two common channels, green1 and green2. [0] [1] [2] [7] x [3] [6] [5] [4] [0] [1] [2] [7] x [3] [6] [5] [4] image optimization vx6953cb 80/107 8209023 rev 5 9.1.5 couplet definition a failing pixel at x with a failing pixel at position [0], [1], [2], [3], [4], [5], [6 ] or [7] such that there is a maximum of two fa iling pixels from the group of nine pixels illustrated in figure 36 . the example shown in figure 36 has the centre pixel and the pi xel at position [7] failing the test criteria. figure 36. general couplet example the basic couplet definition is further subd ivided into minor and major couplets. with respect to the example in figure 36 , a minor couplet is defined as a defect pixel pair where one pixel can be an extreme fail, that is a stuc k at black or stuck at white, but the second pixel in the pair must differ from the local pixel average by less than 25% of that average value. if the second pixel in the couplet differs by more than 25% of the local pixel average value then this would be defined as a major couplet. in addition, couplets will be classified as being in the inner or outer area. 9.1.6 physical aberrations a specific test algorithm is also applied in pr oduction to identify an d reject samples that display defocussed artefacts often referred to as blemishes or shapes. these artefacts are caused by scratches or contamination in the op tical path away from the focal plane that is, on the ir glass or lens. the test requires two regions to be defined: ? a small area: 9 by 9 pixels with the pixel under test at the centre of this area (shaded blue in figure 37 ) ? a large region, 31 by 31 pixels (shaded red in figure 37 ) figure 37. test region definition an average value is calculated for both the ?small? and ?lar ge? areas. the areas are then scanned across each colo r channel separately. [0] [1] [2] [ x ]x[3] [6] [5] [4] 9 pixels 9 pixels 31 pixels 31 pixels small area large area 8209023 rev 5 81/107 vx6953cb image optimization figure 38. scan array for blemish the next stage of the test is the creation of a pixel map for each color channel with the coordinates of the failing pixels. see figure 39 . figure 39. fail map a pixel location is identified as a fail in t he map if it satisfies the following criteria: small_average < large_average - (1.2% of large_average) or small_average > large_average + (1.2% of large_average) the contents of the fail map determines whether the sensor fails the physical aberration test. the module fail criteria is: ? pass if <= 82 contiguous pixel entries in the failure map for each color channel. an example of contiguous pixels entries is given in figure 40 . blemish image optimization vx6953cb 82/107 8209023 rev 5 figure 40. contiguous pixel example 9.2 defect correction the defect correction algorithm dynamically detects and corrects single and couplet defective pixels in the imaging array. the weight of both correction filters can be adjusted. for recommended settings refer to the personality file. an image showing an example of defective pixels is shown below. figure 41. image showing defective pixels a simplified block diagram of the defective correction block is shown in figure 42 . the group of pixels enclosed in the circle are contiguous, that is ever y pixel in the group is attached to at least one neighboring pixel. the other pixel entries shown in the figure are non contiguous as they have no touching neighbors. defective pixels : dead pixels and spikes. couplets : closely located defective pixels (spike or dead pixels). 8209023 rev 5 83/107 vx6953cb image optimization figure 42. block diagram of dy namic defect correction block an example of an image before and after correction is shown in figure 43 . figure 43. dynamic defect correction output example original image corrected image image optimization vx6953cb 84/107 8209023 rev 5 an example of a corrected bayer pattern is shown in figure 44 . figure 44. corrected bayer pattern 9.3 mapped couplet correction (bruce) the mapped couplet de fect correction filter is designed to intelligently correct the first defect in a couplet thereby changing a couplet into a single pixel defect. single pixel defects can then be corrected using the dynamic defect correction filter. the mapped couplet correction filter requires exact coordinate information for each of the couplets to be repaired. the couplet coordinat es are stored in non-volatile-memory (nvm) during production test. the mapped couplet corr ection filter does not operate in binning mode or in subsample mode a nd is automatically disabled. the mapped couplet correction is controlled by register 0x0b05: 0 - disable 1 - enable colorized original bayer colorized corrected bayer 8209023 rev 5 85/107 vx6953cb image optimization 9.4 green imbalance correction since es2.0 modules, the sensor has an adaptiv e (four color temperature) green imbalance correction function which can be used to reduce the green imbalance in the sensor. correction is carried out on the green-blue color plane only. the gain is calculated based on a term polynomial in x and y. in order to optimize the green imbalance corr ection algorithm, the coefficients for each device are calculated under d65 lighting cond itions and programmed in the nvm memory at production test. settings for three other color temperatures (c ool white, tl83, and horizon) are calculated from characterization data and these are stored in the nvm memory. the calculation of the color temperature is performed by the sensor using the color feedback registers. therefore it is necessary for the host to supply the sensor with the white balance gains. the green imbalance correction function can be used with the profile1 and profile 2 scaler and with crop and subsampling. the green imbalance correction is controlled by register 0xfaa3 (0x3410 is the status register): 0 - disable 1 - enable figure 45. green imbalance correction plots original plot corrected plot image optimization vx6953cb 86/107 8209023 rev 5 9.5 lens shading correction the sensor has an onboard adaptive (four color temperature) lens shading correction function which can be used to reduce the effect of roll off in the optical system. correction is carried out individually for all four color planes, each gain is calculated based on the distance from the image centre to the pixel in question using a nine parameterization term (dc offset, x, y, xy, x 2, y2, xy2, x2y, x2y2). in order to optimize the adaptive lens shading algorithm, the coefficients for each device are calculated under d65 lighting conditions and programmed in the nvm memory at production test. settings for three other color temperatures (c ool white, tl83 and horizon) are calculated from characterization data and these are stored in the nvm memory. the calculation of the color temperature is performed by the sensor using the color feedback registers. therefore it is necessary for the host to supply the sensor with the white balance gains. the lens shading function can be used with the profile1 and profile2 scaler and with crop and subsampling. the lens shading correction is controlled by register 0x0b00: 0 - disable 1 - enable the correction applied is 75%. this is meaning image corner re lative illumination = 0.75 * ima ge centre relative illumination. figure 46. lens shading images original image corrected image 8209023 rev 5 87/107 vx6953cb nvm contents 10 nvm contents the sensor has the following contents in the nvm: ? revision and traceability data ? green imbalance correction data ? grid-iron correction data (option) ? sensitivity data (to be used by the host) ? defect data (used on-chip, described in section 9.3 on page 84 ) ? lens shading av2x2 corrector data (used on-chip, described in section 9.5 on page 86 ) 10.1 green imbalance corrector the nvm is programmed with calib ration data for four differen t illuminants that are used by the sensor to minimize green imbalance (used on-chip, see section 9.4 on page 85 ). 10.2 lens shading gridiron correction this data is not used by the sensor but can be used with a host isp based bi-cubic corrector. the lens shading gridiron data is calculated at fmt for each device for one color temperature d65 (fluorescent phillips graphica pro 965). each of the four color channel values are recorded. each grid roi in each color channel with the pedestal removed. the on board lens shading correction is disabled. the analog gain is set to x1. 10.3 sensitivity data this data is not used by the sensor but ca n be used by the host to calibrate the awb system. the sensitivity data is measured at fmt for each device for one color temperature d65 (fluorescent phillips graphica pr o 965). each of the four colo r channel values are recorded. the 10-bit average of the central 1% of the image (1% of image width, 1% of image height) is recorded, the pedestal is included in the va lue. the on-board lens shading correction is disabled. the analog gain is set to x1. more details are provided in the calibration application note. nvm contents vx6953cb 88/107 8209023 rev 5 10.4 nvm map the nvm map is a 512-byte space containing pe r part basis data to optimize the image quality. the nvm map is a delivery do cument that st will supply to customer upon request. note: the sensor must be in software standby to read the nvm. in order to read the nvm the following registers must be programmed. 0x3e04 = 1 - power-up the nvm 0x3640 = 0 - access nvm register space the registers should be reset after reading the nvm to the following: 0x3e04 = 0 - power-down the nvm 0x3640 = 1 - disable access to nvm register space 8209023 rev 5 89/107 vx6953cb emc recommendations 11 emc recommendations the following recommendations should be followed to ensure the emc performance of the device is optimized in its host system. ? the vx6953cb should be sited as far as possible from resonant antenna elements to minimize coupling of rf energy into the camera. ? power supplies should meet ripple requirements, see section 12.3.2: power supply ripple requirement on page 93 . electrical characteristics vx6953cb 90/107 8209023 rev 5 12 electrical characteristics references: ? smia characterization sp ecification - revision 1 ? smia ccp2 specification ecr0002 - revision 1 ? smia ccp2 specification - revision 1 typical values quoted for nominal voltage, pr ocess and temperature. maximum values are quoted for worst case conditions (process, voltage and functional temperature) unless otherwise specified. maximum values are quoted for worst case (process, voltage and test temperature). 12.1 operating conditions ? storage temperature: camera has no permanent degradation. ? functional operating temperature: camera is electrically functional. ? normal operating temperature: camera produces ?acceptable? images. ? optimum performance temperature: camera produces optimal optical performance. ? test temperature: 100% tested parameters are measured at this temperature. table 43. operating conditions symbol parameter min. typ. max. unit voltage vdig digital power supply 1.68 1.8 1.92 v vana analog power supply 2.3 2.8 2.9 v vip(dig) digital input voltage (1) 1. digital input: extclk, xshutdown, scl, sda. 0 - 1.92 v temperature t as temperature (storage) -40 - +85 c t af temperature (functional operating) -30 +70 c t an temperature (normal operating) -25 +55 c t ao temperature (optimal operating) +5 +40 c t at temperature (test) +21 +25 c 8209023 rev 5 91/107 vx6953cb electrical characteristics 12.2 absolute maximum ratings caution: stresses above those listed in section 12.2: absolute maximum ratings may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not imp lied. exposure to absolute maximum rating conditions for extended periods may af fect device reliability. table 44. absolute maximum ratings symbol parameter min. max. unit v digmax digital power supply -0.3 2.2 v v anamax analog power supply -0.3 3.2 v v ihmax extclk, xshutdown, sc l, sda -0.3 vdig+0.5 v t sto storage temperature -40 + 85 (1) 1. this is a maximum long term standard storage te mperature, see soldering profile for short term high temperature tolerance. o c v esd electrostatic discharge model human body model (2) (3) charge device model (4) 2. mm 100v test is performed in compliance with jesd22-a115a if hbm pass level is less then 1000v. 3. hbm tests are performed in compliance with jesd22-a114f. 4. cdm tests are performed in compliance with jesd22-c101d. -2.0 -500 2.0 500 kv v electrical characteristics vx6953cb 92/107 8209023 rev 5 12.3 power supply - vdig, vana 12.3.1 power supply (peak current) - vdig, vana the peak current (in-rush) consumption of th e sensor module is defined as any current pulse >=10 s. the duty cycle of the peak to the low part of the current profile is 33% with a worst-case period of 500 s. table 45. power supplies vdig, vana parameter digital analog unit typ. max. typ. max. hardware standby 10 90 10 135 a software standby: ext. clock not switching ext. clock = 9.6 mhz (1) 1. the digital current scales linearly with the external clock frequency used. 4 6 20 25 0.7 0.7 2.0 2.0 ma ma streaming ccp2: preview (2) capture still (3) 2. binning 2x2 mode, profile 0, 28fps, 10-8 data, edof estimation mode, ccp-2. 3. full resolution image, profile 2, 15fps, 10-8 data, edof application mode, ccp-2 65 90 80 110 55 55 65 65 ma ma streaming csi2: preview (4) capture still (5) 4. binning 2x2 mode, profile 0, 28fps, 10-8 data, edof estimation mode, csi-2. 5. full resolution image, profile 2, 15fps, 10-8 data, edof application mode, csi-2 53 80 80 110 61 62 80 80 ma ma table 46. in-rush current vd ig, vana for ccp2 interface parameter digital analog unit typ. max. typ. max. boot clock peak current (1) 1. this corresponds to the transient current when xshutdown is powered up and the sensor is being set sw_standby mode. max value is given for max vdd and 70c temperature. typical value is for 25c and vdd is set to nominal value. 65 100 170 220 ma start streaming current (2) 2. when the sensor is changed from software sta ndby to streaming mode. max value is given for max vdd and 70c temperature. typical value is for 25c and vdd is set to nominal value. 60 90 170 220 ma stop streaming current (3) 3. when the sensor is changed from streaming to software standby. max value is given for max vdd and 70c temperature. typical value is for 25c and vdd is set to nominal value. 160 190 170 220 ma in streaming mode while changing sensor settings 160 190 90 90 ma 8209023 rev 5 93/107 vx6953cb electrical characteristics 12.3.2 power supply ripple requirement it is recommended that the application meets the following requirements on the power supply signal in 10 khz to 1.4 mhz. table 47. in-rush current vd ig, vana for csi-2 interface parameter digital analog unit typ. max. typ. max. boot clock peak current (1) 1. this corresponds to the transient current when xshutdown is powered up and the sensor is being set sw_standby mode. max value is given for max vdd and 70c temperature. typical value is for 25c and vdd is set to nominal value. 100 140 235 260 ma start streaming current (2) 2. when the sensor is changed from software sta ndby to streaming mode. max value is given for max vdd and 70c temperature. typical value is for 25c and vdd is set to nominal value. 175 210 150 150 ma stop streaming current (3) 3. when the sensor is changed from streaming to software standby. max value is given for max vdd and 70c temperature. typical value is for 25c and vdd is set to nominal value. 175 210 150 150 ma in streaming mode while changing sensor settings 200 240 150 150 ma table 48. ripple requirement symbol parameter max. unit ripple_vana peak to peak max ripple on analogue power supply ( 10 khz to 1.4 mhz ) 6mv ripple_vdig peak to peak max ripple on digital power supply 50 mv electrical characteristics vx6953cb 94/107 8209023 rev 5 12.4 system clock - extclk 12.5 power down control - xshutdown table 49. system clock - extclk symbol parameter min. max. unit leakage current 4 (1) 1. with dc coupled square wave clock. 30 (2) 2. with dc vdig applied. a v cl dc coupled square wave low level 0 0.3 * vdig v v ch dc coupled square wave high level 0.7 vdig vdig+0.5v v v cac ac coupled sine wave 0.5 1.2 v f extclk clock frequency input 6.0 - 1% (3) 3. nominal frequencies are 6.0 to 27 mhz with a 1% centre frequency tolerance. tested at characterization only. 27 + 1% (3) mhz duty cycles clock frequency duty cycles 40 60 % input jitter extclk input jitter - refer to jitter application note (4) 4. st microelectronics will provide upon request an application note detailing the extclk input jitter requirements. ps table 50. power down control - xshutdown symbol parameter min. typ. max. unit v il low level input voltage 0 - 0.3 * vdig v v ih high level input voltage 0.7 * vdig - vana v 8209023 rev 5 95/107 vx6953cb electrical characteristics 12.6 cci interface - sda, scl 12.6.1 cci interface - dc specification 12.6.2 cci interface - timing characteristics table 51. cci interface symbol parameter min. max. unit v il low level input voltage 0 0.3 * vdig v v ih high level input voltage 0.7 * vdig vdig+0.5v v v ol low level output voltage (1) 1. v oh is not valid for cci. 3 ma drive strength. 0 0.2 * vdig v i il low level input current - -10 a i ih high level input current - 10 a table 52. cci interface - timing characteristics symbol parameter min. typ. max. unit t scl scl clock frequency 0 - 400 khz t low clock pulse width low 1.3 - - s t high clock pulse width high 0.6 - - s t sp pulse width of spikes which are suppressed by the input filter 0 - 50 ns t buf bus free time between transmissions 1.3 - - s t hd.sta start hold time 0.6 - - s t su.sta start set-up time 0.6 - - s t hd.dat data in hold time 0 - 0.9 s t su.dat data in set-up time 100 - - ns t r scl/sda rise time 20+0.1 cb (1) - 300 ns t f scl/sda fall time 20+0.1 cb (1) - 300 ns t su.sto stop set-up time 0.6 - - s ci/o input/output capacitance (sda) - - 8 pf cin input capacitance (scl) - - 6 pf 1. cb = total capacitance of one bus line in pf. electrical characteristics vx6953cb 96/107 8209023 rev 5 figure 47. cci ac characteristics all timings are measured from ei ther 0.3 vdig or 0.7 vdig. for further information on the cci interface, re fer to the smia 1.0 part 2: ccp specification document. 12.7 ccp interface 12.7.1 ccp interface - dc specification note: for further information on the sublvds please refer to the smia 1.0 part 2: ccp2 specification document. sda scl t hd.sta t r t high t f t su.dat t hd.dat t su.sta t su.sto ... ... t hd.sta t low t buf stop start stop start 0.7 vdig 0.3 vdig 0.3 vdig 0.7 vdig table 53. ccp interface - dc specification symbol parameter min. typ. max. unit v od differential voltage swing (1) 1. measured over a 100 load. 100 150 200 mv v cm common mode voltage (self biasing) 0.8 0.9 1.0 v r o output impedance 40 140 i dr drive current range (internally set by bias circuit) 0.5 1.5 2 ma psrr (2) 2. nominal value for the interference at v cm voltage through digital supply relative to the interference at digital supply over the 0-1 ghz operating range. psrr = 20*log10 (v dig interference (peak-to-peak) / v cm interference (peak-to-peak)) 0 to 100 mhz - - 30 db 100 to 1000 mhz - - 10 db 8209023 rev 5 97/107 vx6953cb electrical characteristics 12.7.2 ccp interface - timing characteristics the parameters in table 54 are measured across a terminated 100 transmission line. ccp2_signalling_mode register is set to 1, data/strobe mode. figure 48. sublvds ac timing note: for further information on the ccp please refe r to the smia 1.0 part 2: ccp2 specification 30-6-04 document. table 54. ccp interface - timing characteristics symbol parameter min. max. unit f p average data frequency - 640 mbits/s t p average data period 1.56 - ns t jitter (1) 1. t pmax -t pmin . data period jitter - 200 ps t stable both data and clock at the stable level 780 - ps t rise rise time of data+/data-, clk+/clk- 300 400 ps t fall fall time of data+/data-, clk+/clk- 300 400 ps t shew (2) 2. t shew =t cmpshew + t chcshew . total skew between signals - 225 ps t pwr power up/down time - 20 s data+/ data- clk+/ clk- t cmpshew t stable t chcshew t pmin t pmax t fall t rise 80% 0.9v 20% 80% 0.9v 20% electrical characteristics vx6953cb 98/107 8209023 rev 5 12.8 csi-2 interface 12.8.1 csi-2 interface - dc specification ?all rights reserved. this material is reprinted with the permission of the mipi alliance, inc. no part(s) of this document may be disclos ed, reproduced or used for any purpose other than as needed to support the use of the products of stmicroelectronics.? 12.8.2 csi-2 interface - ac specification ?all rights reserved. this material is reprinted with the permission of the mipi alliance, inc. no part(s) of this document may be disclos ed, reproduced or used for any purpose other than as needed to support the use of the products of stmicroelectronics.? table 55. csi-2 interface - high speed mode - dc specification symbol parameter min. typ. max. unit v cmtx hs transmit static common mode voltage 150 200 250 mv v od hs transmit differential voltage (1) 1. value when driving into load impedance anywhere in the z id range (80-125 ). 140 200 270 mv v ohhs hs output high voltage (1) --360mv z os single ended output impedance 40 50 62.5 table 56. csi-2 interface - low power mode - dc specification symbol parameter min. typ. max. unit v oh output high level 1.1 1.2 1.3 v v ol output low level -50 - 50 mv z olp output impedance of lp transmitter 110 - - table 57. csi-2 interface - high speed mode - ac specification symbol parameter min. typ. max. unit data rate 80 - 800 mbits/s t clkp average data period 1.25 - 12.5 ns t r and t f 20% to 80% rise time and fall time 150 - 0.3ui (1) 1. ui is equal to 1/(2*fh) where fh is the fundam ental frequency of the transmission for a certain bit rate. for example, for 600 mbps, fh is 300 mhz. ps t skew data to clock skew -0.15ui - 0.15ui ps table 58. csi-2 interface - low power mode - ac specification symbol parameter min. typ. max. unit t r and t f 15% - 85% rise time and fall time - - 25 ns 8209023 rev 5 99/107 vx6953cb optical specification 13 optical specification 13.1 lens characteristics note: the module ir filter cu t-off wavelength is 650 nm. table 59. typical lens design characteri stics for first source lens supplier parameter value 4 element plastic lens - f/number 2.8 effective focal length 3.32 mm horizontal fov 57.1 in-focus distance range infinity to 40 cm ( edof applied) distortion tv: +/-1% relative illumination (lens only) 48.7% at 1.0 field on green channels. maximum illumination decrease over 10% of image height. (lens only) 8.5% spectral weighting: wavelength (nm) weight 435.8 6 486.1 17 546.1 38 587.6 29 656.3 13 lateral chromatic aberration <1.4 um coating reflectance - all surfaces are coated. at least 50% of all surfaces must fulfil this specification. < 400 nm 400 to 670 nm >670nm no limitation 1.0% absolute, 0.35% avg straight line with a slope of < 3% /100 nm maximum chief ray angle 27.9 optical specification vx6953cb 100/107 8209023 rev 5 13.2 text, 1d and 2d codes reading the vx6953cb camera module features a supermacro mode ( section 8.4: supermacro mode on page 74 ) dedicated to business card and text reading as well as barcode (1d) and 2d qr code reading using a monochrome imag e. refer to application note for detailed image processing optimization. figure 49. barcode and qr code examples the performances in table 60 were achieved on vx6953cb cut 3.0 production limit samples in supermacro mode using st?s image processing pipe and with standard mobile phone application qr decoder software. refer to the edof application note for recommendations on host image processing pipe tuning for qr/barcode reading. table 60. qr code (2d)resolution reading capability performances working distances (cm) qr code 0.339 mm 25 to 28 cm qr code 0.4 mm 20 to 30 cm qr code 0.5 mm 15 to 30 cm qr code 0.6 mm 15 to 30 cm qr code 0.7 mm 15 to 30 cm qr code barcode 8209023 rev 5 101/107 vx6953cb mechanical 14 mechanical 14.1 packaging and delivery this module has been specifically designed to ens ure that the lens barrel is sub-flush to the top surface of the lens mount. st recommends that zero pressure is applied to the top surface of the lens barrel during the assembly processes or by attaching baffles/spacers. if any pressure is applied to the lens barrel surfac e, this could lead to a significant degradation in image sharpness. st?s recommended smop package handling guidelines are available on request. the camera module should not be subjected to any hot manufacturing process as this may lead to degradation of the image performance. any hot manufacturing process performed on the device must be agreed with st, without prior agreement st will not accept liability to any degradation in module performance. figure 50. marking diagram table 61. substrate marking codification line description line one (953c) 953 is the product code c is the die revision line two (plll) p is the assembly plant lll is the b/e sequence line three(ywwa) y is the year ww is the week number a is the module revision pin 1 mechanical vx6953cb 102/107 8209023 rev 5 14.2 inner box labelling the labelling follows the st standard packing acceptance specification. the information on the inner box label is as follows: ? assembly site ? sales type (vx6953cbq05 i/1 or VX6953CBG05I/1) ? quantity ? trace code ? marking ? bulk id number 14.3 packing the vx6953cb packing will be ta pe and reel. st will use a 13? reel and a full reel will contain 600 pieces. orders must be a multiple of the appropriate number with the minimum order size being one full reel. for detailed drawings, request the vx6953cb tape and reel specification documents. 14.4 module outline for details of the mechanical specification for the vx6953cb can be found in the outline drawings available on request from stmicroelectronics. table 62. outline drawing information sales type outline drawing reference vx6953cbq05i/1 adcs 8253333 VX6953CBG05I/1 adcs 8289386 8209023 rev 5 103/107 vx6953cb ordering information 15 ordering information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. table 63. device summary order code package packing vx6953cbq05i/1 smia65 tape and reel VX6953CBG05I/1 smia65 tape and reel user precaution vx6953cb 104/107 8209023 rev 5 16 user precaution as is common with many cmos imagers the camera should not be pointed at bright static objects for long periods of time as permanent damage to the sensor may occur. 8209023 rev 5 105/107 vx6953cb acronyms and abbreviations 17 acronyms and abbreviations table 64. acronyms and abbreviations acronym/ abbreviation definition ccp compact camera port cci camera cont rol interface csi camera serial interface edof extended depth of field emi electromagnetic interference eof end of frame fe frame end fps frames per second fs frame start hwa hardware accelerator i2c inter icbus le line end ls line start lsb least significant byte lvds low voltage differential signalling mbps megabits per second msb most significant byte msp manufacturer specific pixels pck pixel clock pcm pulse code modulation pll phase locked loop ro read only rw read/write smia standard mobile imaging architecture sof start of frame sublvds sub-low voltage differential signalling revision history vx6953cb 106/107 8209023 rev 5 18 revision history table 65. document revision history date revision changes 30-jun-2010 a initial release. 17-jan-2011 b reordered existing chapters and added chapter 14: mechanical on page 101 and chapter 15: ordering information on page 103 . in chapter 3: functional description , updated section 3.4.1: power- up procedure on page 20 and added section 3.4.2: power-down procedure on page 23 . in chapter 4: register map , added registers revision_number_minor, sensor_model_id and sensor_revision_number to table 9: status registers [0x0000 to 0x000f] on page 29 . in chapter 8: edof control , added section 8.5: video modes and edof on page 75 . in chapter 12: electrical characteristics , updated section 12.3: power supply - vdig, vana on page 92 and added duty cycles to table 49: system clock - extclk on page 94 . in chapter 13: optical specification , updated section 13.2: text, 1d and 2d codes reading on page 100 . added that extclk signal has a schmitt-trigger input 10-feb-2011 c redrew figure 24: fifo water mark control on page 61 as original diagram was corrupted when pdf was generated. no technical information has changed. 17-may-2011 d in section 3.4.2: power-down procedure on page 23 , added information on ulps and added figure for power down from streaming. added jitter details to section 12.4: system clock - extclk on page 94 . in section 12.3.1: power supply (peak current) - vdig, vana on page 92 , added details for peak current. removed all 1.2v references due to an issue affecting i 2 c and vdig switch pins. removed man_spec re gister section. other minor corrections and amendments throughout. 05-mar-2013 5 minor updates throughout. 8209023 rev 5 107/107 vx6953cb please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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